United States

In this work, we introduce a physics-informed machine learning framework that can build a model of stochastically behaving defects in the gate oxide of an individual scaled transistor device. This is achieved by automated data-driven analysis of low-voltage stress-induced leakage current data constituting convoluted random telegraph noise signals. The decision-making of the framework is guided by defect physics. Furthermore, it was successfully applied to generate statistics on defect properties in multiple devices.

IRPS 2024 Main Conference

Physics-informed machine learning to analyze oxide defect-induced RTN in gate leakage current

stress-induced leakage current

physics-informed machine learning

oxide defects

bayesian algorithm

random telegraph noise

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Long Read-After-Write-Delay (RAWD) is one of the Show stoppers (S.S) in ferroelectric based VNAND (Fe-VNAND) because of limited read speed. We investigated the RAWD time (tRAWD) in MFIS as well as Laminate-MFIS  (LaMFIS). In LaMFIS, Vt tends to increase slightly at low voltage during Incremental Step Positive Pulse (ISPP) operation. This is caused by the accumulation of trapped electrons at the inserted layer. The novel ISPP scheme removed these electrons and therefore improved device performance.

A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

Due to the demands of AI and HPC, HBM is becoming more high-capacity with multi-die stacks and more complex internal structures. As the number of HBM in SiP also increases, reliability of HBM on SiP has become significant. The main purpose of this study is to compare the structure and stresses of each DUT based on FEA and to analyze the reliability characteristics of HBM by simulating SiP.

Thermo-Mechanical Reliability Characteristics of HBM3

This work presents electromigration (EM) silicon data from realistic power grid device-under-tests (DUT). Power grids featuring logic gate equivalent quasi-load cells were generated by an automatic place-and-route tool to compare the EM failure location and lifetime behaviors. IR drop shifts and voiding location trends inside the grids were measured.

Electromigration Test Chip Experiments From Realistic Power Grid Structures: Failure Trend Comparison and Statistical Analysis

For the first time, we characterize the advanced Black Diamond(R) low-k dielectric and develop a physical model of time dependent dielectric breakdown (TDDB). We use the developed model to explain underlying physical mechanisms responsible for the lifetime degradation from the various integration steps.

Characterization and multiscale modeling of TDDB in state-of-the-art BEOL

Non-destructive failure analysis is often limited to optical methods, which cannot provide the resolution necessary for analyzing state-of-the-art integrated circuits. Here, we present a powerful method based on scanning a single Nitrogen Vacancy center over the sample. This results in quantitative current density maps with high sensitivity and sub-50 nm resolution, detecting for example, open and short circuits. We demonstrate the technology by mapping current flow in a maze of 30 nm wide wires.

Scanning NV Microscopy – Tracing Currents at the Nanometer Scale

In the semiconductor industry, enhancing the hardness of SiO x is an important issue. Previous studies have focused on the oxygen content dependence of hardness only in a limited region close to x = 2, where the hardness generally increases with increasing x. However, our exploration of SiO x revealed a different path to increase hardness: within the subregion 0 &lt; x &lt; 1.2, reducing the oxygen content led to an increase in SiO x hardness.

The Enhancement Mechanisms of SiOx Hardness via Manipulation of Oxygen Content

SRAM SER measurements show a decrease in per-bit susceptibility at the 3-nm FinFET process compared to 5-nm, contrary to the 7-nm to 5-nm trend. Robust data across various supply voltages demonstrates pronounced exponential bias influence on 3-nm FinFET SRAM SER, distinguishing it from earlier processes. Simulation and modeling attribute these trends to Q crit and Q coll variations.

Scaling Trends and Bias Dependence of SRAM SER from 16-nm to 3-nm FinFET

A proper simulation of temperature distributions within the electronic design automation (EDA) flows is quite crucial to achieve both a competitive and reliable design in advanced ICs. This work provides insights into mission profile analysis in foundry business with a strong focus on Electromigration (EM). EDA methodologies that account for local device self-heating, inter-device thermal coupling and temperature-time dependencies are presented and validated by various sign-off scenarios verifying an analog RF power amplifier design.

EDA method to address interconnect reliability and reduce overdesign in custom analog designs

Increasing 3D complexities in modern chipsets necessitate new approaches to fault isolation and post-silicon debug. Recent innovations, including backside power delivery networks and multi-die stacking, impede traditional optical techniques, such as laser-assisted device alteration (LADA). Here we report on the development of a first-of-a-kind x-ray-assisted device alteration (XADA) tool capable of integrating with modern integrated circuit test equipment and demonstrate the use of XADA for real fault isolation and post-silicon debug cases.

Laboratory X-Ray-Assisted Device Alteration for Fault Isolation and Post-Silicon Debug

This paper investigates the alpha- and neutron-induced soft error rate (SER) in SRAMs manufactured with 3 nm bulk gate-all-around (bulk-GAA) process technology. The SER in SRAM of bulk-GAA is maximally 1.56X higher than in the same cell-size SRAM of bulk-FinFET. Moreover, shrinking cell size decreases the SER by a maximum of 0.38X in bulk-GAA. The SER of the minimum-size SRAM in bulk-GAA is lower than in bulk-FinFET.

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Physics-informed machine learning to analyze oxide defect-induced RTN in gate leakage current

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A Comprehensive Study of Read-After-Write-Delay for Ferroelectric VNAND

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