United States

RTN in FinFET at cryogenic temperature is charaterized and RTN caused by traps near Metal/HfO2 interface interacting with gate can be observed, which is often overwhelmed by background noise at room temperature. Combining TCAD, the trap location can be determined. Furthermore, full quantumcalculations and compact modeling considering band tail states and interface trap states are conducted to obtain accurate trap parameters. The results reveal a remarkable variety of traps at cryogenic temperature.

IRPS 2024 Main Conference

New Insights into the Random Telegraph Noise (RTN) in FinFETs at Cryogenic Temperature

finfets

cryogenics

random telegraph noise

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

A novel deep learning-assisted trap extraction method is proposed to extract trap spatial and energetic distribution from the noise power spectral density (PSD). The method comprises two steps: 1) rough extraction using a Convolutional Neural Network and 2) refinement using a Backpropagation Optimization network. This automated approach achieves precise trap extraction with a mean difference as low as 1.5x.  The method is applied to a practical case and successfully extracts the trap distribution.

Deep Learning-Assisted Trap Extraction Method from Noise Power Spectral Density for MOSFETs

We present a characterization methodology for on-resistance and threshold voltage extraction through pulsed IV, where the transition from off-state to measurement phase is tuned to move from soft- to hard-switching. Results demonstrate that: i) RON may show significant increase (with saturation) moving from soft- to hard-switching; ii) VTH is strongly affected by hard-switching; iii) improved passivation results in lower on-resistance increase; iv) gate field plate length impacts RON increase with marginal effect on VTH shift.

Ron and Vth extraction in Hard-Switched E-mode GaN HEMTs: impact of passivation and layout

In this work, we reveal the presence of unique phonon-assisted hot electron transitions during semi-ON state operation of AlGaN/GaN HEMTs resulting in distinct self-heating behavior of the device. This establishes the importance of considering hot electron-triggered transitions, in addition to conventionally considered self-heating sources, while estimating heating effects in these devices. The phenomena are probed through detailed experimentation involving devices with different field plate lengths, electroluminescence microscopy and spectroscopy, and thermal imaging analysis.

Experimental Insights into the Role of Inter-valley and Defect Transitions of Hot Electrons in Determining Self-heating in AlGaN/GaN HEMTs

The reliability issues of the In-3D-NAND approximate searching system for Hamming distance computing are evaluated and solved by optimized high VT level, recovery healing process, and reliability tracking array. The chip with optimized high Vt level can pass the commercial 3D-NAND retention criteria. Recovery healing can mitigate over-program issue in high data update situations. Tracking array enables sensing level calibration for long-term operations. The chip provides reliable in-memory database processing function suitable for neuromorphic computing.

Reliability Assessment for an In-3D-NAND Approximate Searching Solution

This work investigated the statistical modeling for post-programming conductance drift of 3-bit analog RRAM. We proposed a novel criterion, WRMSE, to substantiate that the conductance drift ought to be separated into two distinct phases: relaxation and RTN. We further developed a compact model based on CTMC to capture the variation of post-programming conductance distribution. The established model could provide useful guidelines for the future design of analog-RRAM based neuromorphic computing systems.

Statistical Modeling of Time-Dependent Post-Programming Conductance Drift in Analog RRAM

This talk focuses on aging and self-heating effects in transistors. As technology nodes shrinks, 3D structures become more confined and less reliable. We showcase how deep learning and machine learning techniques offer innovative solutions for the EDA industry. These techniques enable designers to estimate the impact of these phenomena without the need for divulging confidential models. We demonstrate the seamless integration of sign-off tools to estimate self-heating in an entire processor at the GDS level.

Machine Learning Unleashes Aging and Self-Heating Effects: From Transistors to Full Processor

Recent discoveries of ferroelectricity and field-induced ferroelectricity in HfO2 and ZrO2 have led to increased interest in devices based on both materials, enabling a growing number of applications, including high aspect ratio ferroelectric capacitors and field effect transistors. One-transistor/one-capacitor memory arrays of Kbit to Gbit size are reported. From detailed reliability characterization, a complete picture of ferroelectric oxide/metal interface dynamics can be presented, explaining key reliability issues like field cycle endurance and retention.

Ferroelectric HfO2-based Capacitors for FeRAM: Reliability from Field Cycling Endurance to Retention

In this work, we investigated the reversible and irreversible polarization degradation of hafnia-based ferroelectric capacitors (FeCAPs). The main observations are as follows: (1) The temperature-dependent orthorhombic (o-) and tetragonal (t-) structures with coherent phase boundary (CPB) moving corresponds to the reversible polarization changes of hafnia-based FeCAPs with temperature, i.e., the o-t (t-o) coherent structural transition. (2) The polarization degradation caused by o-/m-CPB migration with temperature is irreversible.

Reversible and irreversible polarization degradation of Hf0.5Zr0.5O2 capacitors with coherent structural transition at high temperature

This work investigates the behavior of vth, subthreshold swing , and interface state density of commercial SiC MOSFETs during burn-in process. This study aims to determine the critical stress time to mitigate excessive Vth shift caused by the increase of Dit . The research approach offers insights for optimization of burn-in techniques in the industry, with the objective of reducing shift and preventing the degradation of the intrinsic lifetime of gate oxide while ensuring efficiency.

Evaluation of Burn-in Technique on Gate Oxide Reliability in Commercial SiC MOSFETs

An accelerated self-heating effect (SHE) simulation methodology is presented for GAAFETs, which, in combination with a compact thermal model that considers the geometry dependence of the device, can rapidly evaluate the SHE at the device-circuit level. The compact thermal model of 3nm GAAFET is developed and validated, and SHE can be evaluated in Open Model Interface based on the dynamic time evolution method, which ensures accuracy while significantly improving efficiency without introducing additional circuit nodes.

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New Insights into the Random Telegraph Noise (RTN) in FinFETs at Cryogenic Temperature

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Deep Learning-Assisted Trap Extraction Method from Noise Power Spectral Density for MOSFETs

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