United States

This paper proposes a virtual FA (vFA), a new methodology that helps identify failures in field using the telemetry data. The telemetry data refers to the information that is generated when DRAM product is deployed in customer’s data center and information is generated and collected when faults occur in the field. Through this, risk can be accurately predicted and improvement activities can be carried out quickly.

IRPS 2024 Main Conference

Virtual FA methodology for DRAM: Real-time analysis and prediction method using Telemetry, Field data

failure rate

customer failrue

virtual failure analysis

technical paper

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Cryogenic CMOS circuitry is inevitable to drive and read out qubits for the realization of scalable Quantum Computers (QCs). Analog circuits such as current mirrors and Digital-to-Analog Converter (DAC) are basic building blocks of the control circuits in QCs. In this work, we explore the impact of self-heating (SH) on 5 nm FinFETs and analog circuits for control electronics in QCs using cryogenic-aware BSIM-CMG compact model at both cryogenic and room temperatures.

Impact of Self-Heating in 5 nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction

RTN in FinFET at cryogenic temperature is charaterized and RTN caused by traps near Metal/HfO2 interface interacting with gate can be observed, which is often overwhelmed by background noise at room temperature. Combining TCAD, the trap location can be determined. Furthermore, full quantumcalculations and compact modeling considering band tail states and interface trap states are conducted to obtain accurate trap parameters. The results reveal a remarkable variety of traps at cryogenic temperature.

New Insights into the Random Telegraph Noise (RTN) in FinFETs at Cryogenic Temperature

A novel deep learning-assisted trap extraction method is proposed to extract trap spatial and energetic distribution from the noise power spectral density (PSD). The method comprises two steps: 1) rough extraction using a Convolutional Neural Network and 2) refinement using a Backpropagation Optimization network. This automated approach achieves precise trap extraction with a mean difference as low as 1.5x.  The method is applied to a practical case and successfully extracts the trap distribution.

Deep Learning-Assisted Trap Extraction Method from Noise Power Spectral Density for MOSFETs

In this work, a RTN analysis has been carried out to characterize the defects activated by forward-biased gate stress in GaN-HEMTs with Schottky p-GaN gate. The RTN signal, measured after each stress phase up to time-dependent gate breakdown, revealed four 1/f2 components. Three have been observed on both IG and ID, suggesting defects in the AlGaN barrier, whereas the last one showed up only on IG, possibly related to the Schottky depletion region.

Analysis of RTN Induced by Forward Gate Stress in GaN HEMTs with a Schottky p-GaN Gate

We present a characterization methodology for on-resistance and threshold voltage extraction through pulsed IV, where the transition from off-state to measurement phase is tuned to move from soft- to hard-switching. Results demonstrate that: i) RON may show significant increase (with saturation) moving from soft- to hard-switching; ii) VTH is strongly affected by hard-switching; iii) improved passivation results in lower on-resistance increase; iv) gate field plate length impacts RON increase with marginal effect on VTH shift.

Ron and Vth extraction in Hard-Switched E-mode GaN HEMTs: impact of passivation and layout

We show that thanks to the existence of NBTI, pFETs can be used to build a physical reservoir. We demonstrate this using the Compact-Physical (Comphy) framework for BTI modeling and substantiate it with a gait and voice authentication example. Subsequently, a hardware demonstration reveals that only 9 pFETs are sufficient to distinguish gait signals from different subjects. Notably, this implementation obviates the need for specialized device engineering, allowing for direct utilization of CMOS technology.

Exploiting Bias Temperature Instability for Reservoir Computing in Edge Artificial Intelligence Applications

The reliability issues of the In-3D-NAND approximate searching system for Hamming distance computing are evaluated and solved by optimized high VT level, recovery healing process, and reliability tracking array. The chip with optimized high Vt level can pass the commercial 3D-NAND retention criteria. Recovery healing can mitigate over-program issue in high data update situations. Tracking array enables sensing level calibration for long-term operations. The chip provides reliable in-memory database processing function suitable for neuromorphic computing.

Reliability Assessment for an In-3D-NAND Approximate Searching Solution

Compared to FinFET, MBCFET has significant structural differences such as nanosheet channel with variable width and dielectric spacer between inner gate and highly doped diffusion region. Nanosheet width and spacer architecture play a crucial role in device performance and enable the design of devices with different advantages and disadvantages. We overview the impact of MBCFET 's unique structures on device characteristics and also analyze the reliability impact of MBCFET's unique structures. 

Device Design and Reliability of GAA MBCFET

PBTI for scaled E-Mode High-K GaN-Transistors with ultra-thin Tox &lt; 21.5Å on 300mm diameter GaN-on-Si wafer is studied for the first time. PBTI-degradation rate is shown to decrease over time to reach saturation. Study indicates prevalence of near-interface-traps generated during stress. A phenomenological model is introduced to describe the saturating BTI-degradation dynamics. Despite PBTI-degradation with DVT saturating at ~350mV, the GaN-MOSHEMT Figure-of-Merit gain is projected to be &gt;~15X better than industry-standard Si LDMOS and pGaN-HEMT/GaN-JFET.

PBTI in Scaled Oxide Submicron Enhancement Mode High-K Gallium Nitride Transistors

We show FeFET-based reservoir computing with notable robustness against charge trapping-induced interface degradation in silicon FeFETs, which is known to be critical when operating as nonvolatile memory devices. This reliability concern is mitigated when employed for reservoir computing, which leverages the dynamic property instead of the static property of FeFETs. A degradation-robust FeFET reservoir can be trained to classify spoken-digit dataset, where gt;10k of write operations were applied during data processing, with high classification accuracy.

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Virtual FA methodology for DRAM: Real-time analysis and prediction method using Telemetry, Field data

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Impact of Self-Heating in 5 nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction

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