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In the last decade, we have witnessed an unprecedented revolution of artificial intelligence (AI) as well as various smart devices such as smart phones, AV/VR devices, smart vehicles and robots. Semiconductor is a key player in this revolution as they are at the heart of many inventions related to the computing devices. These transformative trends of AI and smart devices will continue to open up explosive growth opportunities for the semiconductor community. 

IRPS 2024 Main Conference

Innovative Technologies for Sustainable Future of Semiconductor Industry

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#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) will be held in Dallas, Texas from April 14 to 18, 2024. It will be presented as an in-person conference, with a virtual component available.** 

[![](https://assets.underline.io/uploads/markdown_image/1/image/9cc005f94b4ba4a81918eb49e0a51057.png)](https://underline.io/events/446/reception)
[![](https://assets.underline.io/uploads/markdown_image/1/image/acae953ba70ae2a57eed7b0250d6dd7d.png)](https://www.irps.org/)
[![](https://assets.underline.io/uploads/markdown_image/1/image/e1806748f2fc69f825e596872a7afdfd.png)](https://drive.google.com/drive/folders/1SmhpLZD9swYxrfP0TYF6327QTIciy3tV?usp=drive_link)
 

**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**

Please save the zip file locally and click the "start.pdf" to view the file. 
 
**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

To access the site please register [**here**](https://www.irps.org/registration-fees). 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

We develop a new clustering-function-based formulation of the clustering model and successfully apply it for parameter extraction . This new formulation unifies the Weibull model and the clustering into the same mathematical framework but maintains their respective statistical characteristics. With this new parameter extraction methodology, this clustering model can be used to replace the decades-old Weibull model for the assessment of BD data and reliability projection because experimental samples always involve some degree of variability.

A new clustering-function-based formulation of temporal and spatial clustering model involving area scaling and its application to parameter extraction

In this work, we explored the TDDB TTF deterioration under low-frequency of advanced n-FinFETs by analyzing the electrical parameter degradation during the stress. This phenomenon is physically attributable to Maxwell-Wagner instability due to the additional defects generated in IL during the low-frequency AC TDDB stress.

Physical Study of Low-frequency TDDB Lifetime Deterioration in Advanced FinFETs

From over 50 years, dielectric breakdown is a crucial reliability concern in electron devices. Despite various theories accurately replicating breakdown trends in accelerated conditions, discrepancies arise in estimating device lifetime under operating conditions. The latest Carrier Injection (CI) model harmonizes these inconsistencies, revealing dynamic changes in time-to-breakdown E-field dependence. By incorporating trapped charges into CI model, we present a more comprehensive understanding of breakdown, demonstrating that trapped charges enhances reliability by delaying trapping into precursors.

The Major Effect of Trapped Charge on Dielectric Breakdown Dynamics and Lifetime Estimation

After a brief introduction of major categories of optoelectronic devices that will be covered, we’ll start by discussing the main reliability problems that have been encountered in fielded deployment, that we wish to test for. Then we’ll talk about testing at subcomponent and component levels, and different test platforms, as well as how the methods differ from those used in electronic reliability testing. We close with future challenges, and proposals for how to address them.

Reliability Testing for Silicon Photonics and Optoelectronics

In this paper, we present an extensive comparative study of the degradation and recovery kinetics of vertical and lateral-based Ge-on-Si photodiodes. We show that the combination of defects around specific interfaces, in the presence of hot carriers, can lead to localized degradations in the depletion regions. By complementing experimental results with insights from TCAD simulations, we demonstrate the complex interplay between stress, sense conditions, and p-i-n junction types in determining the degradation kinetics.

Degradation and recovery kinetics study of vertical and lateral Ge-on-Si photodetectors

GaN products are now being used for a wide variety of applications, with different types of stresses. Traditional reliability validation and calculations do not cover usage for many types of stresses seen in power supply applications, e.g. those from hard-switching or ringing. There is no adequate methodology, therefore, to calculate lifetime under actual-use conditions. In this paper, we provide a model-based methodology and calculate lifetimes of TI GaN products for usage in a range of...

Mission Profile Approach for the Calculation of GaN FET Reliability in Power Supply Applications

Stability and reliability issues of dynamic ONresistance for Parallel-connected GaN power devices are investigated for the first time. The “550-V-stress/100-V monitor” scheme is used to identify the irreversible dynamic RON degradation. The time-resolved degradation for lifetime evaluation is conducted, where the Parallel-connected devices exhibit a longer operation lifetime as compared with Single device, due to the self-adjustment of the discharging current during the hard switching turn-ON transient.

The First Investigation of Switching Lifetime on Parallel-connected GaN power devices

We present a comprehensive study on the gate stack TDDB challenges in Gate-all-around (GAA) nanosheet (NS) transistors (FETs), including volume-less multi-Vt integration and patterning, the performance and reliability trade-off in inner spacer (IS) module, and the impact from Si channel geometry on gate stack reliability. These scaling associated challenges served as strong motivators and will continue to drive process-reliability co-optimization efforts towards optimum performance while preserving robust TDDB reliability.

Challenges of gate stack TDDB in gate-all-around nanosheet towards further scaling

A comprehensive semi-empirical model is developed to elucidate the dark current dynamics in GaAs/GaAs nano-ridge photodetectors directly grown on 300 mm Si; both constant voltage stress and recovery were investigated. Modeling results greatly agree with the experimental data for all tested stress voltages and temperatures. Leveraging this model, device lifetime and maximum dark current degradation can be estimated for deciding optimal working conditions in different silicon photonic applications. The observations in the recovery phase disclose.

Modeling Dark Current Degradation of Monolithic InGaAs/GaAs-On-Si Nano-Ridge Photodetectors

This work presents a novel experimental setup for dynamic operating lifetime (D-HTOL) and dynamic RON characterization of GaN power transistors on wafer level. The developed methodology allows to induce realistic hard switching stress condition [...]. To demonstrate the effectiveness of the developed methodology, the setup was tested on wafer-level experimental 650 V HEMTs with p-GaN gate. The origin of recoverable degradation processes is discussed by a qualitative model, with reference to buffer and surface trapping.

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