United States

Emulating the cognitive abilities of the brain will enable new paradigms in computing not currently accessible with digital architectures. This poster discusses the use of CMOS circuits in conjunction with devices such as resistive memory (memristors) that mimic the complex synaptic learning modalities found in the brain. System level time-dynamics is examined in the context of spatio-temporal pattern recognition. This research will ultimately advance the capabilities of intelligent computers for sensory processing and control, anomaly detection, and inference and outcome prediction.

https://underline.io/speakers/59511-kurtis-cantley

NSF Workshop on Micro/Nano Circuits and Systems Design

Spiking Neural Circuits for Temporally Dynamic Learning

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


This presentation covers the overview of our NSF medium project and reports on the recent progress including novel deep neural network pruning and quantization methods recently published.

	https://underline.io/speakers/55839-xue-lin

A Unified Software/Hardware Framework of DNN Computation and Storage Reduction Using ADMM

This poster presents a technique to leverage artificial intelligence (AI) to reduce energy transmission in image sensor networks. A multi-task learning analog AI circuit will be embedded in CMOS image sensor to 1) identify relevant frames for transmission; and  2) perform image compression before transmission. Initial measurements results in 65nm process are demonstrated on low-resolution MNIST dataset. The analog AI classifier achieves state-of-the-art energy efficiency.

https://underline.io/speakers/59512-arindam-sanyal

On-chip Multi-Task Learning Analog Artificial Intelligence For Low-Cost Image-Based Environmental Monitoring

I reviewed this NSF CAREER project on deep neural network acceleration using crossbar arrays with resistive random access memory (RRAM). The research accomplishments include several generations of the silicon prototypes including small-scale crossbar array for convolutional kernel (with integrated oscillation neuron), and two generations of compute-in-memory macro with peripheral analog-to-digital converters taped-out in Winbond 90nm RRAM and TSMC 40nm RRAM processes. Another research outcome is the NeuroSim benchmark framework which is an end-to-end simulator to evaluate the deep neural network training/inference accuracy under non-ideal synaptic device properties and to estimate the cycle-accurate and trace-enabled hardware performance including the chip area and energy/latency. I also surveyed future research directions: 1) 3D integration with hybrid technology nodes; 2) ferroelectric transistor as synaptic device; 3) security issues with compute-in-memory. 

https://underline.io/speakers/59513-shimeng--yu

CAREER: Scaling-up Resistive Synaptic Arrays for Neuro-inspired Computing

Information technology has entered the age of heterogeneous computing.  Across a variety of application domains, computing systems rely on highly heterogeneous architectures that combine multiple general-purpose processors with specialized hardware accelerators.  The complexity of these systems, however, threatens to widen the gap between the capabilities provided by semiconductor technologies and the productivity of computer engineers. Embedded Scalable Platforms (ESP) is a new approach to the design and programming of heterogeneous computing systems that raises the level of abstraction in the design process. ESP is an open-source research platform for heterogeneous SoC design that combines a scalable tile-based architecture and a flexible system-level design methodology. Conceived as a heterogeneous integration platform and tested through years of teaching at Columbia University, ESP is naturally suited to foster collaborative engineering of SoC designs across the open-source community.

https://underline.io/speakers/59514-luca-carloni


ESP: The Open-Source System-on-Chip Platform for Heterogeneous Computing

This talk firstly explains why we need to rethink design automation from a hybrid model-based and data-driven perspective, and why we need to extend EDA to multiple engineering domains.  Then I will introduce an uncertainty-aware data-driven design automation framework that can be applied to multiple engineering domains, and explain the shared theoretical challenges. Finally, I will highlight some of our recent theoretical results and demonstrate the applications in electronic IC, photonic IC, autonomous systems and AI systems. 

https://underline.io/speakers/59515-zheng-zhang

Uncertainty-Aware and Data-Driven Design Automation Techniques with Multi-Domain Applications

In recent days, 2.5D package designs have gained popularity with an increasing number of heterogeneous chiplets integrated into advanced system-in-packages. RDL wires become longer and denser, presenting a growing impact on system performance, reliability, and integrity. At present, there exists no standard CAD flow that can design, analyze, and optimize a complete heterogeneous 2.5D system. The traditional die-by-die design approach processes each component independently during extraction and optimization and cannot be applied to heterogeneous systems without fundamental changes in standard CAD tools. Not only the chiplet-package extraction is inaccurate between the die-package interface ignoring all RDL capacitive and inductive impacts, but traditional CAD tools are also unable to perform cross-boundary design optimization. 
We present a complete chiplet-package co-optimization flow for both homogeneous and heterogeneous 2.5D designs. It encompasses 2.5D-aware partitioning, chiplet-package co-planning, holistic and in-context extraction, package inductance consideration, and iterative optimization, along with design analysis and verification of the entire 2.5D system. For homogeneous 2.5D packages, the performance gap to the reference 2D design reduces by 62.5% with our holistic flow. Targeting heterogeneous systems, our in-context design flow achieves less than 1% extraction error on ground and coupling capacitance with comparable design performance.  We further validated our design flow with a design tape-out in TSMC 65nm.

https://underline.io/speakers/59516-yarui-peng

Design, Extraction, and Optimization of Multi-Chip Fan-Out Wafer-Level-Packaging for Low-Power Heterogeneous Systems

The goal of this project is to study the multiphysics, multilevel, multiscale stack of modeling, analysis and optimization from on-chip timing to system reliability under thermal cycling, and develop tools to support system analysis and optimization across this stack. Several recent highlights are presented in the poster.

https://underline.io/speakers/59611-andrew-kahng

SHF: Medium: Closing Multiphysics Analysis Gaps in System Design

This poster introduces a proposed automated design approach for low-cost, turnkey integrated power converters that includes integrated built-in self-test (BIST) to increase the occurrences of first-pass design success. This automation could bridge the gap between the conflicting needs for rapid design cycles and high-performance power electronics seen in applications such as mobile handsets, IoT, and wearables. The goal is to enable rapid design of low-to-medium power converters by developing an automated design platform. By using the BIST monitoring data to update the statistical models used during the design phase, multiple design development cycles could be eliminated and the design risk and non-recurring cost (NRE) could be significantly reduced. It is expected that these closed-loop systems would be successfully automated through creation of analytical models of power converter architectures, development of a circuit component design library and a circuit simulation methodology for collecting a representative subset of design parameters that will correlate to the relevant performance space, creation of statistical models and data that can be used to fit to geometric programming (GP) and support vector machine (SVM) algorithms, and development of a computationally efficient and accurate optimization approach. 

https://underline.io/speakers/59509-jennifer-kitchen

Design Automation Approach for Integrated Power Electronics

In this poster presentation, we present our CAREER project on using 3D integration technology to create a neuromorphic system that is compatible with current technology while providing high system speed, high density, massively parallel processing, low power consumption, and small design area. We plan to develop a comprehensive research program to address the fundamental scientific issues and advanced design challenges involved in building a brain-like computing system using 3D ICs. If successful, the resulting technology could fuel potentially disruptive capabilities in real-time data analysis, time-series predictions, environmental perception for autonomous operations, and dynamic control systems. This technology could also improve the performance of current and future systems by significantly decreasing power, size, and weight budgets, and by enabling embedded and retrofit applications on legacy, mobile, and remote platforms.

https://underline.io/speakers/59612-cindy-yang-yi

Enabling Brain-like Computing through 3D Neuromorphic Circuits and Systems

We present the Chipyard framework, an integrated SoC design, simulation, and implementation framework for specialized compute systems.  Chipyard includes configurable, composable, open-source and generator-based IP blocks that can be used across multiple stages of of the hardware and software development flows, while maintaining design intent and integration consistency.  Through cloud-hosted FPGA-accelerated simulation and rapid ASIC implementation, Chipyard enables continuous validation of physically realizable customized systems.  SoC instances produced from Chipyard have been silicon-verified in TSMC 16nm and Intel 22nm technologies.

https://underline.io/speakers/59613-borivoje-nikolic

Spiking Neural Circuits for Temporally Dynamic Learning

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