United States

The poster presents thermal and power delivery modeling and co-design considerations for emerging 2.5D/3D ICs.

https://underline.io/speakers/59504-muhannad-bakir

NSF Workshop on Micro/Nano Circuits and Systems Design

Electrical-Thermal Co-Design of 2.5D/3D ICs

**IRPS 2024 Tutorials were held in Dallas, Texas from April 14 to 15, 2024. The IRPS Reliability Year in Review (YIR) session consisted of three presentations reviewing the past year's reliability work by experts in the field for areas of high interest. It was a nice augmentation to the tutorials sessions immediately preceding and attendees were able to obtain keen reliability insights in short amount of time.** 

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**[IRPS 2024 eGuide](https://drive.google.com/file/d/1DHxkWbafodK_D2HlDi7lwRK7KatgBgBD/view?usp=drive_link)**
Please save the zip file locally and click the "start.pdf" to view the file. 

**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Tutorials and YIR

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

poster

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


While the proliferation of electronics has been driven by computing and consumer applications for a long time, integrated circuits (ICs) presently undergo accelerated integration into healthcare, transportation, robotics, and autonomous systems. In addition to provision of prescribed functionalities of sensing, computing, and processing, these ICs must meet stringent reliability specifications in order to safeguard performance and safety of the whole mission-critical system where deployed. Circuits designed to be fail-safe by design exhibit low occurrences of failure. However, having a sign of no failure under typical verification and test procedures yields no guarantee for meeting a given near-zero or extremely-low failure specification. On the other hand, exhaustiveness may never be achieved by brute-force failure detection, which results in an unacceptably high cost in simulation and testing. This project will develop efficient machine-learning techniques for extremely-rare circuit-failure detection without needing large amounts of expensive simulation or test data. The proposed techniques will enable cost-effective verification and test of reliability-critical ICs and mission-critical systems in general. The research undertaken will also enable the two groups at UC Santa Barbara and UT Dallas to educate and train undergraduate and graduate students, including women and underrepresented groups, thus expanding the and contributing to the much needed US technological workforce.

It is believed that extracting critical failure information via machine learning within practical limits of available measurement or simulation data can go a long way towards extremely rare failure detection. This project centers on developing an active-learning framework that intelligently samples in the high-dimensional space of complex interacting design parameters, manufacturing variations, and operating conditions, achieving the goal of data-efficient detection of rare circuit failures. The targeted active-learning framework will be supported by the development of machine-learning model foundations and robust learning methods that can scale to high-dimensional parameter spaces. The key objective of this project is to make extremely-rare failure discovery and identification of the underlying failure mechanisms practically viable by extracting the maximum amount of useful information possible from a small amount of available data. The proposed extremely-rare failure discovery work will be broadly applicable to verification and failure analysis of analog, mixed-signal, radio-frequency, and memory circuits with stringent failure specifications and many other types of mission-critical systems.

This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.

https://underline.io/speakers/59522-hanbin-hu

Collaborative Research: SHF: Medium: Data-Efficient Uncovering of Rare Design Failures for Reliability-Critical Circuits

Biological neural networks process streams of temporal information at efficiencies and proficiencies well exceeding those of man-made systems. Recent work in understanding brain dynamics from the point of view of machine learning is starting to demystify the mechanisms behind their extraordinary performance. By distilling these mechanisms in neuromorphic technologies, the prospect of practical brain-like processing at the edge is becoming real. However, the tools at the disposal of neuroscientists and engineers to prototype and train such models are still inadequate. In this poster, I explain the potential rewards and challenges of training biological neural networks, namely Spiking Neural Networks (SNNs). I will provide the roadmap for the solutions to these problems, which build on an exciting combination of autodifferentiation techniques and dynamics inspired by neurobiology. 

https://underline.io/speakers/59505-emre-neftci

Scalable Neuromorphic Learning Machines

Our CAREER research aims to developing novel computing systems exploiting Three-Independent-Gate Field Effect Transistors (TIGFETs), a novel device technology capable of device-level functionalities typically not achievable by standard CMOS and leading to major benefits at gate and circuit levels. A TIGFET is capable of dynamic reconfiguration of its polarity. In order to fully assess the potential of this technology, we are demonstrating: (1) the fabrication, characterization and modeling of TIGFETs using advanced semi-conductor materials, (2) the development of a complete design framework for TIGFETs, including a design kit, novel circuit primitives and dedicated design tools, and (3) the evaluation of TIGFET-enabled systems.

https://underline.io/speakers/59506-pierre-emmanuel-gaillardon

Functionality-enhanced Devices for Extending Moore's Law

Deep neural networks (DNNs) have gained widespread applications in numerous applications, especially for embedded and Internet-of-Things (IoT) devices. Nowadays on-device DNN inference has been extensively investigated because of its inherent advantages on data privacy, response time and bandwidth demand than cloud-based inference. On the other side, on-device DNN learning, which also has very strong practical demands and owns the similar advantages over the cloud-based training, however, has not been widely studied yet due to the dilemma between expensive training cost and limited on-device resource.  To address this challenge and promote the further deployment of on-device learning, this project proposes to leverage low-rank tensors, as a powerful mathematical tool for representing and compressing tensor-format data, to achieve real-time energy-efficient DNN learning on the device. 

https://underline.io/speakers/59507-bo-yuan

TensorNN: An Algorithm and Hardware Co-design Framework for On-device Deep Neural Network Learning using Low-rank Tensors

Machine learning is the key to sustaining the economic growth in many sectors within the U.S. science and engineering enterprise. Neuromorphic architectures that mimic biological neurons and synapses can execute machine learning algorithms in an energy-efficient manner, allowing for their integration with the internet-of-things, another industry sector projected to have an economic impact of more than $1 trillion by 2025. However, neuromorphic architectures are fundamentally unreliable. They introduce errors during execution, limiting the dependability of machine learning and impeding their technological progress. This project will address dependability challenges of neuromorphic computing, by looking at all levels, from building error-resilient machine learning algorithms to designing fault-tolerant hardware. This project will advance the field by 1) making neuromorphic computing reliable, efficient, programmable, and easy-to-use for the community, 2) teaching future science and engineering students how to make machine learning algorithms error-resilient, 3) creating job opportunities in neuromorphic industry through national and international internships and collaborations, 4) raising interest of high school students in STEM through neuromorphic computing enabled robotics workshops, and 5) building an integrated neuromorphic community through a new focused conference on neuromorphic computing.

https://underline.io/speakers/59508-anup-das

Facilitating Dependable Neuromorphic Computing: Vision, Architecture, and Impact on Programmability

We present and investigate a novel application domain for deep reinforcement learning (RL): droplet routing on digital microfluidic biochips (DMFBs). A DMFB, composed of a two dimensional electrode array, manipulates discrete fluid droplets to automatically execute biochemical protocols such as point-of-care clinical diagnosis. However, a major concern associated with the use of DMFBs is that electrodes in a biochip can degrade over time. Droplet-transportation operations
associated with the degraded electrodes can fail, thereby compromising the integrity of the bioassay outcome. We show that casting droplet transportation as an RL problem enables the training of deep network policies to capture the underlying
health conditions of electrodes and provide reliable fluidic operations. We propose a new RL-based droplet-routing flow that can be used for various sizes of DMFBs, and demonstrate reliable execution of an epigenetic bioassay with the RL droplet router on a fabricated DMFB. To facilitate further research, we also present a simulation environment based on the OpenAI Gym Interface for RL-guided droplet-routing problems on DMFBs.

https://underline.io/speakers/60045-krishnendu-chakrabarty

Adaptive Droplet Routing in Digital Microfluidic Biochips Using Deep Reinforcement Learning

Emulating the cognitive abilities of the brain will enable new paradigms in computing not currently accessible with digital architectures. This poster discusses the use of CMOS circuits in conjunction with devices such as resistive memory (memristors) that mimic the complex synaptic learning modalities found in the brain. System level time-dynamics is examined in the context of spatio-temporal pattern recognition. This research will ultimately advance the capabilities of intelligent computers for sensory processing and control, anomaly detection, and inference and outcome prediction.

https://underline.io/speakers/59511-kurtis-cantley

Spiking Neural Circuits for Temporally Dynamic Learning

This presentation covers the overview of our NSF medium project and reports on the recent progress including novel deep neural network pruning and quantization methods recently published.

	https://underline.io/speakers/55839-xue-lin

A Unified Software/Hardware Framework of DNN Computation and Storage Reduction Using ADMM

This poster presents a technique to leverage artificial intelligence (AI) to reduce energy transmission in image sensor networks. A multi-task learning analog AI circuit will be embedded in CMOS image sensor to 1) identify relevant frames for transmission; and  2) perform image compression before transmission. Initial measurements results in 65nm process are demonstrated on low-resolution MNIST dataset. The analog AI classifier achieves state-of-the-art energy efficiency.

https://underline.io/speakers/59512-arindam-sanyal

On-chip Multi-Task Learning Analog Artificial Intelligence For Low-Cost Image-Based Environmental Monitoring

I reviewed this NSF CAREER project on deep neural network acceleration using crossbar arrays with resistive random access memory (RRAM). The research accomplishments include several generations of the silicon prototypes including small-scale crossbar array for convolutional kernel (with integrated oscillation neuron), and two generations of compute-in-memory macro with peripheral analog-to-digital converters taped-out in Winbond 90nm RRAM and TSMC 40nm RRAM processes. Another research outcome is the NeuroSim benchmark framework which is an end-to-end simulator to evaluate the deep neural network training/inference accuracy under non-ideal synaptic device properties and to estimate the cycle-accurate and trace-enabled hardware performance including the chip area and energy/latency. I also surveyed future research directions: 1) 3D integration with hybrid technology nodes; 2) ferroelectric transistor as synaptic device; 3) security issues with compute-in-memory. 

https://underline.io/speakers/59513-shimeng--yu

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