Due to their inherent characteristics regarding sensitivity and flexible design, Giant Magnetoresistance (GMR) based sensors are the preferred option for the measurement of low magnetic fields within small volumes (electronic compass, bio-magnetism, non-destructive testing…) 1. In addition, GMR devices have demonstrated their compatibility with different standard technologies (such as CMOS) and other emerging ones (such as microfluidics) 2, so broadening their fields of application. For example, GMR sensors have been successfully used as currents sensors in integrated circuits and also as bio-detectors for different specimens in Lab-on-chip systems. More recently, GMR elements have been proposed as basic detectors in neuromorphicaly approached magnetic field imaging sensors, for potential applications in biotechnology and testing. The design and optimization of this kind of system demand electrical models which are compatible with conventional microelectronics design tools 3. In this sense, partial solutions have been proposed, providing static, noise and thermal models, mainly for discrete components applications in electrical current sensing 4.
In this work, the development of a compact dynamic electrical model for GMR sensors is described. The Verilog-A high-level description language has been considered in order to provide a useful model for being used in conventional CMOS design tools, such as Cadence Virtuoso. The model includes the proper blocks for alternate current and transient analysis, which are mandatory by the high speed related to the design of neuromorphicaly approached imaging sensors. Functional parameters were obtained from specifically designed sensors including single resistors, voltage dividers and full bridges (see Fig. 1). The schematic of the model for the single resistor sensor is depicted in Fig. 1. Fig. 2 displays preliminary impedance results comparing experimental measurements with model-predicted behaviour for a frequency sweep in the range of interest. Fig. 2 also includes transient modelling for the voltage divider topology.