Magnetic Tunnel Junctions (MTJ) are one of the major building blocks of spintronics, used in random access memory designs due to non-volatility, endurance and fast switching. Regardless of the choice of writing scheme, e.g Spin-Transfer Torque (STT)1 or Spin-Orbit Torque (SOT)2, we need to tailor the intrinsic properties of the switchable magnet (the Free Layer) in order to ensure a high retention time of the magnetization state, representing a trade off with respect to the switching energy, i.e the more retention, the more energy required to operate the device. To overcome the dilemma and enable MTJs with high retention and low writing energy, a Hybrid Free Layer (HFL) concept has been previously proposed by integrating a Synthetic Antiferromagnet (SAF) stack into the widely used CoFeB/MgO Free Layer stack3. This HFL has two intrinsic interlayer couplings tailored by a SAF and SFM (synthetic ferromagnet) spacers (Fig. 1). The SAF spacer reduces the stray field and gives an exchange coupling torque from the motion of either layer II or III, leading to faster overall motion of the stack. The SFM spacer allows for flexibility in the choice of SAF design, as it couples the layer I directly to layer II, but also decouples the crystallization of the Tunneling Barrier interface from layer II, preventing lattice mismatching effects and bad electronic band conditions in a wide range of materials4. This work explores this design focusing on compensation of ground states (where the stack adds up to no field). We demonstrate by micromagnetics that adding a SFM to a SAF stack impacts the energy and layer trajectories in non-trivial ways. For instance, in Fig. 2 the hysteresis loop of HFL stacks with both compensated equilibrium states and Top Major (layers I, II generate field) show that even at compensation point we have degeneracy of states, i.e regions of external field where both low/high energy states are stable. This contrasts with SAF only stacks where outside of compensation a behavior towards saturation is observed (Fig.2 Right). Different switching speeds can also be found by tailoring the coupling strengths.
References
1 S. Sakhare et al., 2018 IEEE IEDM; 2 S. Couet et al., 2021 Symposium on VLSI Technology, 2021, pp. 1-2. 3 E. Raymenants et al., Nature Electronics, volume 4, pgs 392–398 (2021). 4 Liu, E. et al., IEEE Trans. Magn. 53, 1–5 (2017).

Fig.1 HFL design with top MTJ.

Fig. 2 HFL (left) and SAF (right) hysteresis loops.