United States

Magnetic random access memory (MRAM) is a promising candidate for beyond-CMOS memory and logic technologies and has been developed for commercial purposes in recent years (1). The key building block of commercial MRAM is magnetic tunnel junction (MTJ), which is operated through either spin transfer torque (STT) or spin-orbit torque (SOT). STT-based MRAM benefits from higher cell density but suffers from reliability and energy-efficiency due to the current flow through the MTJ whereas SOT-based MRAM has superior reliability, endurance, and faster switching times (2). For realizing the ultralow switching current density and ultrafast switching MRAM cell, two or more driving forces are normally employed to switch MTJs. One acts as the principal switching mechanism and the other serves to assist in switching. For example, ultrafast switching speed of ~ 0.27 ns has been reported in SOT switching of perpendicular MTJs (p-MTJs) assisted with STT and voltage-controlled magnetic anisotropy (VCMA), however, the key challenge is still large switching current densities (Jc) ~ 2.0×108 A/cm2 for SOT and ~ 2.3×106 A/cm2 for STT (3).
Voltage controlled exchange coupling (VCEC) occurs in perpendicular MTJs (p-MTJs) with synthetic antiferromagnetic (SAF) free layers and can realize bidirectional switching at switching current densities as low as 1 x 105 A/cm2 (4). In this work, we designed and fabricated the p-MTJ stacks with SAF free layers on bi-layered spin Hall channels (Ta/Pd). The p-MTJ stacks were patterned into 150-nm pillars, and MTJ devices are switched through combination of SOT and VCEC effects, as illustrated in Fig. 1(a). Bidirectional switching of p-MTJs were obtained with current densities as low as 3×103 A/cm2 for VCEC and 6.8×107 A/cm2 for SOT, as shown in Fig. 1(b), where the VCEC switching current density is two orders of magnitude lower than the reported value for VCEC-only switching [4]. Furthermore, by studying the contribution of SOT and VCEC for MTJ switching, it is found that SOT plays a crucial role for ultralow-energy VCEC bidirectional magnetization switching.&lt;br&gt;

**References:**&lt;br&gt;
(1) J.-P. Wang et al, DAC &#39;17: Proceedings of the 54th Annual Design Automation Conference 16, pp. 1-6 (2017).&lt;br&gt;
(2) Y. C. Liao et al, IEEE J. Explor. Solid-State Computat. 6, pp. 9-17 (2020).&lt;br&gt;
(3) E. Grimaldi et al, Nat. Nanotechnol. 15, pp. 111-117 (2020).&lt;br&gt;
(4) D. Zhang et al, Nano Lett., 22, pp. 622-629 (2022).&lt;br&gt;

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MMM 2022

Ultra low current density switching via voltage

Magnetic random access memory (MRAM) is a promising candidate for beyond-CMOS memory and logic technologies and has been developed for commercial purposes in recent years (1). The key building block of commercial MRAM is magnetic tunnel junction (MTJ), which is operated through either spin transfer torque (STT) or spin-orbit torque (SOT). STT-based MRAM benefits from higher cell density but suffers from reliability and energy-efficiency due to the current flow through the MTJ whereas SOT-based MRAM has superior reliability, endurance, and faster switching times (2). For realizing the ultralow switching current density and ultrafast switching MRAM cell, two or more driving forces are normally employed to switch MTJs. One acts as the principal switching mechanism and the other serves to assist in switching. For example, ultrafast switching speed of ~ 0.27 ns has been reported in SOT switching of perpendicular MTJs (p-MTJs) assisted with STT and voltage-controlled magnetic anisotropy (VCMA), however, the key challenge is still large switching current densities (Jc) ~ 2.0×108 A/cm2 for SOT and ~ 2.3×106 A/cm2 for STT (3).
Voltage controlled exchange coupling (VCEC) occurs in perpendicular MTJs (p-MTJs) with synthetic antiferromagnetic (SAF) free layers and can realize bidirectional switching at switching current densities as low as 1 x 105 A/cm2 (4). In this work, we designed and fabricated the p-MTJ stacks with SAF free layers on bi-layered spin Hall channels (Ta/Pd). The p-MTJ stacks were patterned into 150-nm pillars, and MTJ devices are switched through combination of SOT and VCEC effects, as illustrated in Fig. 1(a). Bidirectional switching of p-MTJs were obtained with current densities as low as 3×103 A/cm2 for VCEC and 6.8×107 A/cm2 for SOT, as shown in Fig. 1(b), where the VCEC switching current density is two orders of magnitude lower than the reported value for VCEC-only switching [4]. Furthermore, by studying the contribution of SOT and VCEC for MTJ switching, it is found that SOT plays a crucial role for ultralow-energy VCEC bidirectional magnetization switching. 

**References:** 
(1) J.-P. Wang et al, DAC '17: Proceedings of the 54th Annual Design Automation Conference 16, pp. 1-6 (2017). 
(2) Y. C. Liao et al, IEEE J. Explor. Solid-State Computat. 6, pp. 9-17 (2020). 
(3) E. Grimaldi et al, Nat. Nanotechnol. 15, pp. 111-117 (2020). 
(4) D. Zhang et al, Nano Lett., 22, pp. 622-629 (2022). 

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poster

#### Welcome to the 67th Annual Conference on Magnetism and Magnetic Materials, MMM 2022!

The Conference was held from October 31 to November 4 and offers both in-person and on-demand content.

MMM 2022 is sponsored jointly by AIP Publishing and the IEEE Magnetics Society. Members of the international scientific and engineering communities interested in recent developments in fundamental and applied magnetism are invited to attend and contribute to the technical sessions. The technical program will include invited and contributed papers in oral and poster sessions, invited symposia, a tutorial, and several special sessions. This Conference provides an outstanding opportunity for worldwide participants to meet their colleagues and collaborators and discuss developments in all areas of magnetism research.

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Racetrack memory is expected to be a memory device that supports the information society because of its high speed and low power consumption. Although many studies have been conducted to improve the speed of magnetic domain wall movement, few studies have been conducted from the viewpoint of Joule heat. Therefore, we have investigated the relationship between Joule heat and domain wall motion in the 2022 Joint MMM-INTERMAG.(1) 
In elucidating the mechanism of this current-driven domain wall motion, although the domain wall width is an essential parameter for improving the domain wall moving speed and the critical current density, the details of the domain wall width are still unknown. Generally, MFM is used for magnetic domain observation. In MFM, as shown in FIG. 1, it is possible to observe the magnetic domain shape by vibrating a thin magnetic needle up and down, but it is challenging to investigate the accurate magnetic flux density distribution. However, suppose the TMR head can be contacted with the sample and scanned. In that case, the distance between the sample and the TMR head can be kept constant to measure the accurate magnetic flux density distribution created by the magnetic recording domain. FIG. 2 shows a TMR head scan image of a magnetic domain recorded in a racetrack memory having a width of 10 μm and a length of 100 μm. The result of line scanning by enlarging this domain wall is also shown in the figure. The recording material is TbCo ferrimagnetic material, the domain wall movement is fast, and the critical current density is small (2). Despite the small saturation magnetization due to ferrimagnetism and thin film (10 nm), the TMR head could measure a clear change in magnetic flux density within a range of ± 20 mT. 

**References:** 
(1) Sota, K. et al. Relationship between pulse width and domain wall velocity in current induced domain wall motion in GdFeCo wire and the effect of joule heat on the racetrack memory, Joint MMM-Intermag Conference, 3628926 (2022) 
(2) Sina, R. et al. Fast Current Induced Domain Wall Motion in Compensated GdFeCo Nanowire, Joint MMM-Intermag Conference, 3786257 (2022) 

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Evaluation of magnetic flux density distribution of magnetic domains recorded in racetrack memory by TMR head

Unidirectional spin Hall magnetoresistance (USMR) is a magnetoresistance effect with potential applications to read two-terminal spin-orbit-torque (SOT) devices directly. In this work, we observed a large USMR value (up to 0.710-11 per A/cm2, 50% larger than reported values from heavy metals) in sputtered amorphous PtSn4/CoFeB bilayers. Ta/CoFeB bilayers with interfacial MgO insertion layers are deposited as control samples. The control experiments show that increasing the interfacial resistance can increase the USMR value, which is the case in PtSn4/CoFeB bilayers. The observation of a large USMR value in an amorphous spin-orbit-torque material has provided an alternative pathway for USMR application in two-terminal SOT devices. 

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Observation of unidirectional spin Hall magnetoresistance in amorphous PtSn4/CoFeB bilayers

L10-ordered MnAl, a perpendicularly magnetized film material, has attracted much attention due to its high magnetic anisotropy, low saturation magnetization, and low magnetic damping for spin-transfer-torque magnetic random access memory (STT-MRAM) applications. However, in magnetic tunnel junctions (MTJs) with a single MnAl ferromagnetic layer, the TMR ratio has not been confirmed. This is due to the large lattice mismatch between MgO tunneling barrier and MnAl layer, which prevents the coherent tunneling of Δ1 electrons (1). In this work, we utilized Co-doped MnAl and MgAl2O4 tunneling barrier to reduce lattice mismatch and inserted a very thin Fe layer into (MnCo)Al/MgO interface to improve TMR effect.
The structure of the MTJs prepared in this study is shown in Fig.1. The MTJ films were prepared using the ultrahigh vacuum magnetron sputtering method. (MnCo)Al layers with low roughness and high (001) orientation by adding 2% Co. The composition of MgAl2O4 was measured using X-ray photoelectron spectroscopy (XPS). Compositional analysis showed that the composition of MgAl2O4 was Mg : Al : O =9.2 : 18.9 : 41.5 (atom%). MTJ devices were microfabricated and characterized their TMR properties by DC 4-probe method.
We succeeded in observing a TMR ratio of 8% at 300K without an insertion layer by using (MnCo)Al electrode and MgAl2O4 tunneling barrier as shown in Fig. 2(a). In addition, TMR ratio was improved to 9.4% by insertion of ultra-thin Fe layer into the (MnCo)Al/MgO interface as shown in Fig. 2(b). This translates to 18.8% in terms of magnetization parallel state. Since the RA product was decreased from 1.2 MΩμm2 to 223 kΩμm2 by insertion of Fe, coherent tunneling process was thought to be promoted by the interfacial modification.
This work was supported by the Center for Advanced Spintronics Research and Development, the Center for Spintronics Cooperative Research and Education and Development, and the Center for Spintronics Cooperative Research and Education, Tohoku University. 

**References:** 
(1) H.Saruyama, M.Oogane, Y.Ando, 2013, Jpn. J. Appl. Phys., 52, 063003 

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Dependence of TMR and RA on Fe insertion layer thickness in MTJs using L10 (MnCo)Al electrode and MgAl2O4 insulating layer

Magnetoresistive sensors have been enthusiastically selected for applications requiring magnetic field detection with sensors combining small footprint (1), highly linear response curves with low coercivity and low field detectivities. From the viable alternatives (2), MgO-based magnetic tunnel junctions (TMR) offer very competitive performance values, as sensitivity as large as 300 %/mT are reported (3). The optimization of the sensor response includes using soft magnetic free layers, based on CoFeB and NiFe alloys (4).
Here we report the performance of TMR sensors including CoFeBTa and CoFeBSi soft magnetic films as free layers (FL). Magnetic tunnel junction stacks based on (Ta 5/Ru 10)x3/Ta 5/Ru 5/MnIr 8/CoFe 2.2/Ru 0.65/CoFeB 2/MgO/CoFeB/FL2/cap (nm) (fig. 1) were grown on 200 mm wafers using a combination of ion beam and magnetron sputtering deposition from the 14 targets available in the machine. The TMR stacks were magnetically characterized by vibrating sample magnetometry and CIPT, while microfabricated devices (rectangular shaped pillars of varying areas and aspect ratios) were evaluated for transfer curve sensitivity, linear range and noise.
The magneto-crystalline anisotropy, Hk, was assessed for CoFeBTa and CoFeBSi films, with values of 2.1 and 5.3 mT measured for 4 nm films integrated in the TMR stacks. Although these values are larger than for single NiFe FL (1.7 mT)(fig. 2), the global performance of the CoFeBTa/CoFeBSi-based sensors is improved, with magnetoresistance of 210 %, when comparing with 190 % (CoFeB) or 150 % (NiFe). Field sensitivities up to 80 %/mT are obtained, with similar hysteresis (Hc) as for CoFeB or NiFe stacks.
The low frequency noise (1/f dominated) characteristic was evaluated for the microfabricated devices. As an example, sensors with FL2 = CoFeBTa (10 TMR elements connected in series) provided Hooge factor αH = 2.4x10-10 μm2 and detectivity levels of D = 4.5 nT/√Hz at 10 Hz. These values are aligned with previously reported values with similar materials (4).
Acknowledgments: FCT grant UI/BD/151461/2021 

**References:** 
(1) M. Silva, D.C. Leitão, S. Cardoso and P. P. Freitas, IEEE Trans. Magn. 53, 7762720 (2017) 
(2) C. Zheng et al., IEEE Trans. Magn. 55-4, pp. 1-30 (2019) 
(3) TMR9001, MultiDimension Technology, Datasheet available online: http://www.dowaytech.com/en/1866.html (accessed on 24 June 2022) 
(4) M. Rasly et al., J. Phys. D: Appl. Phys. 54, 095002 (2021) 

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CoFeBX layers for MgO based magnetic tunnel junction sensors with improved noise and detectivity

Spintronics-based devices offer certain key advantages like ease of fabrication with Si-substrate, non-volatile memory, low operational voltage, and non-linear device characteristics. Hardware security is a research domain that heavily relies on CMOS-based ICs, and the defense and attack mechanism is developed accordingly.
In this work, we explore shape anisotropy-based PMA Double barrier MTJ based on Verilog-A behavioral model (1) to design a possible Logic locking (2) system for Hardware Security. Logic Locking is a widely used security mechanism to counter multiple threats (3). Due to larger free layer thickness, the s-PMA DMTJ has better thermal stability even in the sub-10nm dimension. The current work focuses on Logic locking applications using this device, analyze its behavior under process variation in certain key parameters using Monte-Carlo simulations, and finally performs Eye-diagram performance analyses to test the design for high-speed digital logic applications. The results indicate that the s-PMA DMTJ has good thermal stability, smaller size (10nm dimension), robustness to device imperfections, and ability to work in high-speed digital circuits compared to other emerging MTJ structures such as STT MTJ, SOT MTJ, VG-SOT MTJ, etc.
Fig. 1(a) represents the block diagram of the logic Locking block, and Fig. 1(b) represents the circuit for implementing the desired operation. We have performed electrical simulations in TSMC 40nm CMOS generic process design kit using the cadence specter simulator with W/L ratio = 3, the temperature at 300K. Fig. 2(a) and 2(c) represent some circuit performance comparisons like the Eye-diagram test for high-speed circuits, and Table 1 presents the simulation data for the same. Fig. 2(b) shows that VG-SOT MTJ (4) fails the eye-diagram test for similar applications for comparison with s-PMA DMTJ. 

**References:** 
(1) H. Wang et al., “Modeling and Evaluation of Sub-10-nm Shape Perpendicular Magnetic Anisotropy Magnetic Tunnel Junctions,” IEEE Transactions on Electron Devices, vol. 65, no. 12, pp. 5537-5544, Dec. 2018. 
(2) H. M. Kamali, K. Z. Azar, F. Farahmandi, and M. Tehranipoor, “Advances in Logic Locking: Past, Present, and Prospects,” Cryptology ePrint Archive, 2022. 
(3) S. Bhunia, and M. Tehranipoor, “Hardware security: a hands-on learning approach,” 1st Edition, 2018. 
(4) K. Zhang, D. Zhang, C. Wang, L. Zeng, Y. Wang and W. Zhao, “Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction,” IEEE Access, vol. 8, pp. 50792-50800, 2020. 
(5) K. Watanabe et al., “Shape anisotropy revisited in single-digit nanometer magnetic tunnel junctions,” Nature Communication, 2018. 

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Double Barrier s PMA MTJ

With the rapid growth of technologies such as the Internet of Things (IoT) and artificial intelligence (AI) in recent years, giant data transmission and processing capacities of computers have faced major hurdles (1, 2). At the moment, memory is the key bottleneck in computer processing big data processes. The CPU and the memory are distinct in the standard Von Neumann design, while frequent data exchange uses a lot of energy, resulting in the "Memory Wall" problem (3). On-chip cache, being the crucial constituent of CPU, accounts for a pivoltal portion of the system's overall power consumption. If the power wastage of the on-chip cache could be lowered, the ultimate performance of the CPU can be strengthened. The typical SRAM-based cache is vulnerable to high static leakage power consumption, and scaling up its capacity is challenging. Magnetic random access memory (MRAM) (4), as a new non-volatile storage technology, is expected to break the limitation at the cache level (5).
In the paper, MRAM cache is used to limit static leakage power consumption. A quad-core CPU MRAM hierarchical cache system is established in the designed MRAM cache, with the high-speed Spin-Orbit-Torque (SOT)-MRAM (6) functioning as the L1 cache and the high-density Spin-Transfer-Torque(STT)-MRAM (7) serving as the L2 shared cache. A non-inclusive allocation method is adopted for the data-exchange strategy, by which the number of the write operation in the L2 STT-MRAM cache is reduced, and the energy consumption of the system is further reduced. The designed system is simulated and verified based on gem5 (8) software framework. The simulation results show that strategy of the hybrid MRAM memory is a promising candidate for high-speed and low-power on-chip cache. 

**References:** 
(1) Y. Li, Z. Wang, R. Midya et al., Journal of Physics D: Applied Physics., vol. 51, p.503002(2018) 
(2) J.-M. Hung, X. Li, J. Wu et al., IEEE Transactions on Electron Devices., vol. 67, p.1444-1453(2020) 
(3) X. Huang, C. Liu, Y.-G. Jiang et al., Chinese Physics B., vol. 29, p.078504(2020) 
(4) M. Durlam, P. J. Naji, A. Omair et al., IEEE Journal of Solid-State Circuits., vol. 38, p.769-773(2003) 
(5) F. Oboril, R. Bishnoi, M. Ebrahimi et al., IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems., vol. 34, p.367-380(2015) 
(6) K. Jabeur, L. D. Buda-Prejbeanu, G. Prenat et al., International Journal of Electronics Science and Engineering., vol. 7, p.501–507(2013) 
(7) D. Apalkov, A. Khvalkovskiy, S. Watts et al., ACM Journal on Emerging Technologies in Computing Systems., vol. 9, p.13:1–13:35, (2013) 
(8) N. Binkert, B. Beckmann, G. Black et al., ACM SIGARCH computer architecture news., vol. 39, p.1-7(2011) 

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Hierarchical Cache Configuration Based on Hybrid SOT and STT

Spin-transfer-torque magnetic random-access memory (STT-MRAM) is one of the promising emerging memory technologies as it offers high speed and non-volatility required for embedded applications such as SOCs, IOTs, and Microprocessors (1).However, due to the magnetic nature of the STT-MRAM, the free layer of the memory cell is sensitive to the external magnetic field and the thermal fluctuation (2). For the practical application scenarios of STT-MRAM, the memory may be exposed to high external magnetic field for short time. In this way, high immunity is required for the STT-MRAM memory to avoid any possible data errors caused by the external magnetic field.
In the paper, the memory model at array level is established to study the immunity property of STT-MRAM. By investigation on the magnetic field distribution of the memory array under different external magnetic field, the three operation modes, including standby, active read and active write modes, are simulated and analyzed. Based on the simulation results, the immunity property and the reliability of the memory array is discussed and optimized.
The paper is organized as follows. Firstly, the STT-MRAM array model is established in the HFSS. The magnetic field distribution in the memory array is simulated. The influences of the key geometrical parameters on the magnetic distribution, including the thicknesses of the epoxy and the electrode layer, are investigated. Secondly, to improve the immunity property of the memory, the approach of adding high permeability magnetic shield material is proposed in the paper. Thirdly, the influence of the magnetic immunity on the data reliability of the memory is investigated. The reliability is basically all about data retention and it is determined by effective Eb (3). And the bit error rates (BERs) of the MTJs under the states of standby, active read and active write, are also analyzed in the paper.
Fig.1 The established array model of the STT-MRAM for the immunity investigation. (a) The magnetic field distribution of STT-MRAM array. (b) The magnetic distribution in single STT-MRAM cell. 

**References:** 
(1) B. Bhushan, L. T. Guan, D. Shum et al., 2018 IEEE International Memory Workshop (IMW), p. 1-4, (2018). 
(2) S. Srivastava, K. Sivabalan, J. H. Kwon, et al. Applied Physics Letters, 114(17):172405. (2019). 
(3) T. Y. Lee, K. Yamane, L. Y. Hau, et al. 2020 IEEE International Reliability Physics Symposium (IRPS). p. 1-4 (2020). 

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High reliability of STT MRAM with enhanced magnetic immunity

Spin transfer torque magnetoresistive RAM (STT-MRAM) is one of the promising emerging memory technologies, with the merits of CMOS-compatibility, fast read speed, high density and non-volatile, etc. (1). However, the write speed is one of the major challenges for STT-MRAM, especially in high speed applications. For a reliable writing operation, high writing current and enough duration time are required, which could decrease the life-time of the tunnel layer in the MTJ device and cause extensive power consumption. So, the writing strategy of the STT-MRAM is one of the key issues in the memory design. Several writing strategies are proposed to improve the writing reliability, lower the power consumption, as well as increase the life-time of the device.
In the paper, the pipeline structure combined with the parallel shift register circuit is proposed to achieve the high write efficiency for the STT-MRAM. Figure 1 shows the block diagram of the proposed multi-bit parallel pipeline-circuit. In the designed circuit, the introduction of bit-parallel processing is essential to achieve high throughput operation (2).The parallel shift register circuit is added in the STT-MRAM to allow serial data to be transferred to the sensing circuit in parallel. Moreover, the pipeline structure is also utilized in the peripheral circuit. Several latches operating in response to a clock signal to process the data by dividing the write operation into a plurality of stages (3). Thus, the multi-bit parallel data can be carried out in pipelining manner, greatly increasing the average write speed and the throughput of STT-MRAM. The proposed write strategy of STT-MRAM achieves better write efficiency and high throughput, which has potential high speed application of STT-MRAM in the future.
Fig.1 The block diagram of the proposed multi-bit parallel pipeline-circuit design for STT-MRAM. 

**References:** 
(1) K. Huang, R. Zhao, N. Ning, et al., IEEE Trans. Circuits Syst., vol. 61, p. 2614-2623 (2014). 
(2) R. Kashima, I. Nagaoka, M. Tanaka, et al. IEEE Trans. Appl. Supercond., vol.99, p. 1-1 (2021). 
(3) Y. Ma, S. Miura, H. Honjo, et al., Jpn. J. Appl. Phys., vol. 59, p. SG (2020). 

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Novel multi bit parallel pipeline

Spintronic devices driven by spin-orbit torque (SOT) have a lot of potential for future neuromorphic computing hardware platforms. Nevertheless, problems such as multistate loss, weight time-dependent variability, and output discontinuity ensue when the device size is reduced to the nanoscale, which is contradictory to the needs of traditional high-precision neural networks. In this study, we propose a high-precision all-spin neural network based on magnetization switching of a simple nanoscale multi-functional SOT device. The all-spin neural network is implemented by the Binary Weight Network, in which binary synapse is encoded by the two states formed by the device's deterministic switching and the practical neuron is realized by its stochastic switching probability. Furthermore, we use a difference derivation training algorithm for the general-purpose network in a novel way to be more compatible with the discontinuous neuron output. Using this strategy, our network recognition accuracy can reach ~81.73% on the universal CIFAR-10 dataset, paving the way for the practical hardware implementation of nanoscale SOT devices in high-precision compact neuromorphic computing. 

**References:** 
J. Zhou, T. Zhao and J. Chen, Advanced Materials., Vol. 33, p.2103672 (2021) 
S. Zhang, J. Zhang and L.You, Science China Information Sciences., Vol. 65, p.1-9 (2022) 

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Binary weight network utilizing multi functional spin

We report the experimental demonstration of long-range orbital torques generated by Nb and Ru and detected by spin-torque ferromagnetic resonance (ST-FMR) measurements in Nb/Ni and Ru/Ni bilayers. We identify the orbital torques from the sign-reversal and a strong enhancement in the damping-like torque observed in Nb (Ru)/Ni bilayers as compared to Nb (Ru)/FeCoB bilayers as theoretically predicted1. The long-range nature of orbital transport in the ferromagnet was revealed by varying the thickness of Ni in Nb (Ru)/Ni bilayers which is markedly different compared to the regular spin absorption in the ferromagnet that takes place in the first few layers confirming the recent prediction2. Finally, we show that the external injection of orbital current in a heavy metal such as Pt can convert the orbital current into a spin-current leading to higher switching efficiency and the enhanced spin-current generation that could both be potentially attractive for the application3,4. 
**References** 1. Go, D. & Lee, H.-W. Orbital torque: Torque generation by orbital current injection. Phys. Rev. Res. 2, 013177 (2020).
2. Go, D. et al. Long-Range Orbital Magnetoelectric Torque in Ferromagnets. arXiv 2106.07928, 1–6 (2021).
3. Ding, S. et al. Harnessing Orbital-to-Spin Conversion of Interfacial Orbital Currents for Efficient Spin-Orbit Torques. Phys. Rev. Lett. 125, 177201 (2020).
4. Go, D., Jo, D., Lee, H.-W., Kläui, M. & Mokrousov, Y. Orbitronics: Orbital currents in solids. EPL (Europhysics Lett. 135, 37001 (2021).
5. 
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