technical paper

MMM 2022

November 07, 2022

Minneapolis, United States

Time domain Computing for Boolean Logic using STT

Spin transfer torque magnetic random access memory (STT-MRAM) shows great advantages for computing-in-memory (CIM) 1. Time-domain (TD) in-MRAM computing can be implemented with unlimited signal accumulation and low power consumption characteristics thanks to its low precision 3. In this paper, we propose a novel TD-CIM topology that converts bit-line (BL) voltage to time delay. Fig.1 (a) shows the structure of proposed STT-MRAM for TD-CIM. Fig.1 (b) illustrates the proposed AND/OR/Full-Adder (FA) Boolean logic circuit, with one transistor-one magnetic tunnel junction (1T-1MTJ) bit-cell. RP/RAP (parallel and anti-parallel magneto-resistance) is with data ‘0’/‘1’. During computation mode, word-line (WL) activates two bit-cell within one row. The calculation-line (CL) generates differential VBL according to the state of bit-cell. Current starved inverters (CSI) circuit is used to convert the voltage of BL to time delay 4. The inverter chains (REF0/REF1) generate delay to represent data ‘0’/1’ for FA logic, which is controlled by signal Cin. Time-to-Digital converter (TDC) converts CSI outputs from time domain to digital domain. The inverter chains generate reference delay for AND/OR/FA logic. CSI outputs sample the reference delay by D-flip-flop (one flip-flop for AND/OR, three flip-flops and one Multiplexer for FA). The performance is analyzed with a 28-nm CMOS process and a MTJ compact model 5. Fig.2 (a) demonstrates the simulated 500 runs Monte-Carlo analysis of CSI outputs under different cases. Results show the successfully distinguished CSI accumulation. The power consumption of AND/OR and FA is 7.89-μW and 14.1-μW at nominal 0.9V supply (see Fig. 2(b)). Fig.2 (c) shows the computation accuracy of AND/OR/FA logic in varied tunnel magnetoresistance ratio (TMR) with different data cases. When TMR=200%, 94.2% to 100% computation accuracy can be obtained, whereas the accuracy is deteriorated when TMR equals to 125%.

References 1 M. Wang et al., Nature Communications, vol. 9, p. 671 (2018). 2 X. Fong et al., IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 22, pp. 384–395 (2014). 3 P. -C. Wu et al., IEEE International Solid- State Circuits Conference (ISSCC), pp. 1-3 (2022). 4 Q. -K. Trinh et al., IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 65, no. 10, pp. 3338-3348 (2018). 5 Y. Wang et al., IEEE Trans. on Electron Devices, vol. 63, pp. 1762-1767 (2016).


Transcript English (automatic)

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