United States

In this work, we introduce N-polar HEMTs on single crystal aluminum nitride (AlN) substrates with a GaN/AlGaN/AlN heterostructure. The homoepitaxially grown AlN layer and the N-polar structure offer many advantages over the conventional Ga-polar AlGaN/GaN HEMTs, such as high breakdown voltage, superior thermal management, stronger electron confinement, and low-resistivity ohmic contact. The first DC results of the device will be presented, and these results will help guide us in creating high performance RF HEMTs with minimal thermal issues.

DRC 2022

First demonstration of N-polar GaN/AlGaN/AlN HEMT on Single Crystal AlN Substrates

hemt

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC), which will be held during the same week, from June 20-23. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

![](https://assets.underline.io/uploads/markdown_image/1/image/eb26c24a18d5d1030616afa4f993cf89.png)
	
<a href="https://www.mrs.org/docs/default-source/meetings-events/mrs-conference-services/2021/emc-2021/2021-emc-program-at-a-glance-6-16-21.pdf?sfvrsn=e39f950c_4">Latest Program-at-a-Glance</a>

<a href="https://drive.google.com/file/d/1eiS1ao4p83VNy8xgHs3Rls7gTQjx7Rc4/view?usp=sharing">Full Program with Abstracts</a>

EMC 2021

technical paper

[![](https://assets.underline.io/uploads/markdown_image/1/image/985c8a40b04e56675221c8549975de3c.png)](https://drive.google.com/file/d/1B70nPIeeeqdG4UU70NlYXuKVOHLRuJEo/view?usp=sharing)

### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

### **Topics**
* Biological Devices
* Devices for Extreme Conditions
* Heterogeneously Integrated Devices
* Memory Devices
* Modeling and Simulation of Devices
* Nanoscale and Vacuum Devices
* Optoelectronic and Optical Devices
* Other Emerging Devices
* Power Devices
* Quantum Devices
* RF and Terahertz Devices
* Spintronic and Magnetic Devices
* Thin-film Devices
* Wide-bandgap Devices
 
### **Invited Speakers**
* Patrick Fay, University of Notre Dame
* Susanne Hoffmann-Eifert, Peter Grünberg Institute
* Sanghyeon Kim, Korea Advanced Institute of Science and Technology
* Sriram Krishnamoorthy, University of California, Santa Barbara
* Mario Lanza, King Abdullah University of Science and Technology
* Xiuling Li, The University of Texas at Austin
* Marko Radosavljevic, Intel Corporation
* Siddharth Rajan, The Ohio State University
* Giordano Scappucci, Delft University of Technology
* Fisher Yu, University of Arkansas
* Wenjuan Zhu, University of Illinois at Urbana-Champaign




Registration is required to attend this event. If you have not already done so, please use the link below to register for a ticket to the conference:

https://www.mrs.org/drc-2022/registration

Registration Is Required

DRC continues to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an article in the Journal of the Electron Device Society. 
DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

A new approach of pulsed current-voltage (I-V) protocol has been applied that reveals current settling. This protocol minimizes metal-FE interface charging and directly reveals amplitude-dependent polarization continuation. Measurement of electroresistance ratio shows it is possible to detect opposite-state or same-state polarization, but not without partial polarization change.

Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory Implications for Partial State Storage

Two-dimensional (2D) materials and their heterostructures are promising for memristive applications due to their extreme scalability and high performance.1 Threshold switching in 2D-Transition Metal Dichalcogenide (TMDC) memristors has been previously identified for neuromorphic applications.2 On the other hand, accurate control of defect concentration in 2D-TMDC films is necessary for optimized performance of the memristive devices. In this work, we explore a chemical route to control defect concentration in 2D-MoS2 films. We demonstrate that the defect concentration in 2D-MoS2 can be tuned by H2O2 treatment. We then optimize the resistance switching behavior of Au/MoS2/Ag/Au memristors to obtain reliable threshold resistance switching with high on/off ratio, low operating voltages and self-compliance behavior. This work offers promise for a low-cost, scalable approach to develop 2D-TMDC based high-performance neuromorphic hardware.

Controllable Defect Engineering in 2D-MoS2 for high-performance threshold switching memristive devices

In this research, we investigated the effect of low sputtering power for 5 nm thick ferroelectric nondoped HfO2 gate insulator formation to improve the operation speed and operation voltage of scaled MFSFET. Sputtering power of 50 W for 5 nm thick ferroelectric nondoped HfO2 gate insulator formation was effective not only to increase the memory window but also to reduce the low frequency noise spectral density of MFSFET with the improvement of interface property.

Ultrathin Ferroelectric Nondoped HfO2 for MFSFET with High-speed and Low-voltage Operation

This work proposes a cryogenic memory array utilizing ferroelectric SQUID as the memory and heater cryotron as the access device. The lack of a suitable and scalable cryogenic memory is one of the major bottlenecks for implementing large-scale quantum computers and superconducting circuits and systems. Our proposed cryogenic memory can solve the scalability issue of the existing superconducting memories without imposing any additional constraint on the performance.

Cryogenic Memory Array based on Ferroelectric SQUID and Heater Cryotron

Cryogenic computing requires extensive memory and bandwidth. Capacitor-less single transistor DRAM offers larger capacity along with improvement in retention characteristics at cryogenic temperatures. Thyristor RAM (TRAM), in addition to having FinFET form-factor compatibility, benefits from a large on/off ratio (>10^7) and non-destructive read that enable a fast read/write speed (<1ns). In this paper, through TCAD simulations a TRAM is demonstrated for cryogenic applications for the first time and its performance metrics are compared to FB-PDSOI capacitorless-DRAM at cryogenic temperature. A permanent 'data 1' retention and more than 10^5s 'data 0' retention time is observed at 77K.

Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing

Due to the better electrostatic control, semiconductor industry has already adopted gate-all-around FETs (GAAFETs) for upcoming technology nodes. Effects like sub-band quantization, threshold voltage shift, the geometry-dependent density of states (DOS) etc., are predominant in the terminal characteristics of GAAFETs due to strong geometrical confinement, which has a significant impact on both analog and RF characteristics of the device. In this paper, for the first time we demonstrate the impact of corner rounding radius (rc) on quantum confinement effects which alter the sub-band quantization levels of the channel. We have used a 2D Schrödinger solver to obtain the sub-band energy levels and used BSIM-CMG framework to predict the effect of sub-band quantization on the terminal characteristics of the device viz. capacitances, drain currents and transconductances with respect to rc variations.


Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes

In this work, we revisit the L-BTBT GIDL in GAA nanowire FETs and propose design guidelines for amplifying the hole accumulation and floating body effects for realizing scalable 1T-DRAM with large sense margin, high retention and low write energy. The proposed NWFET based 1T-DRAM exploiting L-BTBT GIDL for write operation exhibits an ultra-low write energy of 7.3 fJ, high sense margin of 88.4 nA and a retention time of 0.1 ms even for an ultra-short gate length of 20 nm.

Revisiting Gate-Induced Drain-Leakage in Nanowire FETs for 1T-DRAM

In this work, we present the thermal impedance characterization and modeling for 5nm node FinFET devices for the first time. Considerable difference in iso-thermal frequencies ( 𝑓𝑖𝑠𝑜) for n- (∼5 GHz) and p-type (∼2.5 GHz) devices is a crucial experimental observation. Calibrated SPICE simulation shows a 40-70 °C rise in the temperature.

Self-Heating characterization and modeling of 5nm technology node FinFETs

we have developed a compact model for Trap Assisted Tunneling (TAT) based GIDL leakage, and highlighted that only BTBT (Band-to-Band-Tunneling) is not
enough to capture the physical trends of GIDL, and TAT is the essential physical mechanism at the advanced technology
nodes.

Compact Model for Trap Assisted Tunneling based GIDL

We presented a geometry-scalable thermal resistance 𝑅𝑡ℎ modeling approach for AlGaN/GaN HEMTs based on the industry-standard ASM-HEMT compact model. Three different gate peripheries (4 × 100 𝜇𝑚, 4 × 125 𝜇𝑚, and 6 × 100 𝜇𝑚) were used for this work and the value of 𝑅𝑡ℎ was extracted using the coincidence method. The derived dependence with device width was modeled empirically and incorporated in the ASM-HEMT model which resulted in a scalable DC and RF model for AlGaN/GaN HEMTs.


First demonstration of N-polar GaN/AlGaN/AlN HEMT on Single Crystal AlN Substrates

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Next from DRC 2022

Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory Implications for Partial State Storage

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Exploring Al(X)Ga(1-X)N Nanostructures Fabricated via Top-Down Chemical Wet Etching

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First demonstration of N-polar GaN/AlGaN/AlN HEMT on Single Crystal AlN Substrates

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Next from DRC 2022

Pulsed Current-Voltage Protocol to Reveal Polarization-Continuation in Ferroelectric Memory Implications for Partial State Storage

Similar lecture

Exploring Al(X)Ga(1-X)N Nanostructures Fabricated via Top-Down Chemical Wet Etching

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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