United States

Cryogenic computing requires extensive memory and bandwidth. Capacitor-less single transistor DRAM offers larger capacity along with improvement in retention characteristics at cryogenic temperatures. Thyristor RAM (TRAM), in addition to having FinFET form-factor compatibility, benefits from a large on/off ratio (&gt;10^7) and non-destructive read that enable a fast read/write speed (&lt;1ns). In this paper, through TCAD simulations a TRAM is demonstrated for cryogenic applications for the first time and its performance metrics are compared to FB-PDSOI capacitorless-DRAM at cryogenic temperature. A permanent &#39;data 1&#39; retention and more than 10^5s &#39;data 0&#39; retention time is observed at 77K.

DRC 2022

Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing

cryogenic computing.

tram

capacitor-less dram

thin-capacitively-coupled-thyristor

**Please view our Welcome to MH21 video.**

<center>
<figure class="video_container">
	 <iframe src="https://screencast-o-matic.com/watch/cr1UYHV1pcz?v=6&ff=1&title=0&controls=1" width=826 height=526 frameborder="0" allowfullscreen="true"> </iframe>
</figure>
	</center>


**Walkthrough Video**

Here is a Walkthrough showing how to navigate the conference and network with others 

<center>
<figure class="video_container">
	 <iframe src="https://screencast-o-matic.com/watch/cr1vnrV1paE?v=6&ff=1&title=0&controls=1" width=826 height=526 frameborder="0" allowfullscreen="true"> </iframe>
</figure>
	</center>




	 Organized by
 
<a href="https://mrs.org.sg/">
<img src="https://assets.underline.io/uploads/markdown_image/1/image/95d5789689d5f900b90e9fe54ea3cf0d.jpg"</a>

 
	
	 In association with
 
<a href="http://www.ntu.edu.sg/">
<img src="https://assets.underline.io/uploads/markdown_image/1/image/334cd171ad2fdee033c635b368e5e160.png"</a>
	<a href="https://www.nus.edu.sg/">
<img src="https://assets.underline.io/uploads/markdown_image/1/image/32e6f82c0440f7bb24c590f9f67821bd.png"</a>
		<a href="https://www.a-star.edu.sg/">
<img src="https://assets.underline.io/uploads/markdown_image/1/image/72557865b589cfa3d2a0243ffce4a270.png"</a>
	
 


	 Supported by
 
		 <a href="https://www.visitsingapore.com/mice/en/about-us/about-secb/">
<img src="https://assets.underline.io/uploads/markdown_image/1/image/6e679842ead62be522ba6a630b82d5c9.png"</a>

To access the MH 21 Conference, [please register](https://mh21.mrs.org.sg/event/da3f9651-429f-4763-81b2-ebd7311b6bc8/websitePage:206f7605-1731-41f9-8421-56d3890f398f)

MATERIALS FOR HUMANITY (MH 21)

MH 21 is arranged around 6 themes that focus attention on pressing needs that should be addressed to enhance the well-being of communities and provide a forum for presenting breakthrough discoveries.

Cryogenic computing requires extensive memory and bandwidth. Capacitor-less single transistor DRAM offers larger capacity along with improvement in retention characteristics at cryogenic temperatures. Thyristor RAM (TRAM), in addition to having FinFET form-factor compatibility, benefits from a large on/off ratio (>10^7) and non-destructive read that enable a fast read/write speed (<1ns). In this paper, through TCAD simulations a TRAM is demonstrated for cryogenic applications for the first time and its performance metrics are compared to FB-PDSOI capacitorless-DRAM at cryogenic temperature. A permanent 'data 1' retention and more than 10^5s 'data 0' retention time is observed at 77K.

poster

[![](https://assets.underline.io/uploads/markdown_image/1/image/985c8a40b04e56675221c8549975de3c.png)](https://drive.google.com/file/d/1B70nPIeeeqdG4UU70NlYXuKVOHLRuJEo/view?usp=sharing)

### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

### **Topics**
* Biological Devices
* Devices for Extreme Conditions
* Heterogeneously Integrated Devices
* Memory Devices
* Modeling and Simulation of Devices
* Nanoscale and Vacuum Devices
* Optoelectronic and Optical Devices
* Other Emerging Devices
* Power Devices
* Quantum Devices
* RF and Terahertz Devices
* Spintronic and Magnetic Devices
* Thin-film Devices
* Wide-bandgap Devices
 
### **Invited Speakers**
* Patrick Fay, University of Notre Dame
* Susanne Hoffmann-Eifert, Peter Grünberg Institute
* Sanghyeon Kim, Korea Advanced Institute of Science and Technology
* Sriram Krishnamoorthy, University of California, Santa Barbara
* Mario Lanza, King Abdullah University of Science and Technology
* Xiuling Li, The University of Texas at Austin
* Marko Radosavljevic, Intel Corporation
* Siddharth Rajan, The Ohio State University
* Giordano Scappucci, Delft University of Technology
* Fisher Yu, University of Arkansas
* Wenjuan Zhu, University of Illinois at Urbana-Champaign




Registration is required to attend this event. If you have not already done so, please use the link below to register for a ticket to the conference:

https://www.mrs.org/drc-2022/registration

Registration Is Required

DRC continues to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an article in the Journal of the Electron Device Society. 
DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Due to the better electrostatic control, semiconductor industry has already adopted gate-all-around FETs (GAAFETs) for upcoming technology nodes. Effects like sub-band quantization, threshold voltage shift, the geometry-dependent density of states (DOS) etc., are predominant in the terminal characteristics of GAAFETs due to strong geometrical confinement, which has a significant impact on both analog and RF characteristics of the device. In this paper, for the first time we demonstrate the impact of corner rounding radius (rc) on quantum confinement effects which alter the sub-band quantization levels of the channel. We have used a 2D Schrödinger solver to obtain the sub-band energy levels and used BSIM-CMG framework to predict the effect of sub-band quantization on the terminal characteristics of the device viz. capacitances, drain currents and transconductances with respect to rc variations.


Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes

In this work, we revisit the L-BTBT GIDL in GAA nanowire FETs and propose design guidelines for amplifying the hole accumulation and floating body effects for realizing scalable 1T-DRAM with large sense margin, high retention and low write energy. The proposed NWFET based 1T-DRAM exploiting L-BTBT GIDL for write operation exhibits an ultra-low write energy of 7.3 fJ, high sense margin of 88.4 nA and a retention time of 0.1 ms even for an ultra-short gate length of 20 nm.

Revisiting Gate-Induced Drain-Leakage in Nanowire FETs for 1T-DRAM

In this work, we present the thermal impedance characterization and modeling for 5nm node FinFET devices for the first time. Considerable difference in iso-thermal frequencies ( 𝑓𝑖𝑠𝑜) for n- (∼5 GHz) and p-type (∼2.5 GHz) devices is a crucial experimental observation. Calibrated SPICE simulation shows a 40-70 °C rise in the temperature.

Self-Heating characterization and modeling of 5nm technology node FinFETs

we have developed a compact model for Trap Assisted Tunneling (TAT) based GIDL leakage, and highlighted that only BTBT (Band-to-Band-Tunneling) is not
enough to capture the physical trends of GIDL, and TAT is the essential physical mechanism at the advanced technology
nodes.

Compact Model for Trap Assisted Tunneling based GIDL

We presented a geometry-scalable thermal resistance 𝑅𝑡ℎ modeling approach for AlGaN/GaN HEMTs based on the industry-standard ASM-HEMT compact model. Three different gate peripheries (4 × 100 𝜇𝑚, 4 × 125 𝜇𝑚, and 6 × 100 𝜇𝑚) were used for this work and the value of 𝑅𝑡ℎ was extracted using the coincidence method. The derived dependence with device width was modeled empirically and incorporated in the ASM-HEMT model which resulted in a scalable DC and RF model for AlGaN/GaN HEMTs.


A width-scalable SPICE compact model for GaN HEMTs including self-heating effect

UV-LEDs are in demand for their sterilization properties. Tunnel junction UV-LEDs while solving several challenges of conventional UV-LEDs also provides a method to realize cascaded LEDs. Multi-active region UV-LEDs can enable EQE scaling, multi-wavelength emission and high output power density at reduced cost leading to commercially viable LEDs. Efficient multi-active regions can be achieved by low voltage drop tunnel junctions and optimized active regions. In this work, we demonstrate for the first time, a dual-junction UV-LED, with transparent tunnel junctions.

Multi-Active Region AlGaN Ultraviolet Light Emitting Diodes with Transparent Tunnel Junctions

Low-cost and easily integrable mid-infrared (MIR) sources are highly desired for photonic integrated circuits. Thermal incandescent MIR sources are widely used. They work by Joule heating, i.e. an electrical current through the emitter causes thermal emission according to Planck’s law. Their simple design with only two contact pads makes them integrable with typical optoelectronic components in high-volume production flows. Graphene’s emissivity is comparable to common metallic emitters. In contrast to the latter, graphene is transparent at MIR wavelengths, which enables placing large area graphene emitters in the evanescent field of integrated waveguides. This enhances emission by near-field coupling directly into the waveguide mode, avoiding the mode-mismatch to free space. Here, we present the first experimental demonstration of a graphene emitter placed directly on a photonic waveguide, hence emitting directly into the waveguide mode.

Graphene waveguide-integrated thermal infrared emitter

2D materials have gained attention for their resistive switching (RS). Platinum diselenide (PtSe2) stands out because it can be grown at CMOS back-end-of-line compatible temperatures and has excellent long-term stability. We present the first detailed study on forming free RS in PtSe2-based memristors using CMOS-compatible electrodes. We performed 45 bipolar switching cycles on four devices, finding a consistent switching ratio of 9. Excellent retention characteristics confirm the non-volatility of the RS for more than 3 days and 22 hours.

Non-Volatile Resistive Switching in PtSe2-Based Crosspoint Memristors

Heterojunctions made of 2D materials provide promising properties for the realization of tunnel transistors. We demonstrate band-to-band tunneling between layers of WSe2 and MoS2 contacted with few-layered graphene on both sides of the junction and completely encapsulated with hexagonal boron nitride. We also use graphene as a gate electrode, allowing us to realize devices made entirely of different 2D materials. We observe negative differential resistance confirming the tunneling transport in our devices without using any high-k dielectric or chemical doping.

Tunneling transport in WSe2-MoS2 heterojunction transistor enabled by a two-dimensional device architecture

We for the first time report GFETs with 2nm crystalline CaF2 as a gate insulator. We perform the analysis of device-to-device variability and hysteresis dynamics in these devices before and after annealing at 175C. Our results suggest that the counterclockwise hysteresis observed in some devices is due to adsorbates as it can be suppressed by high-temperature treatment. The remaining clockwise hysteresis is record-small which suggests that CaF2 contains much fewer insulator defects as compared to amorphous oxides like SiO2 or Al2O3. Thus, CaF2 is a very promising insulator for 2D electronics.

Cryo-TRAM: Gated Thyristor based Capacitor-less DRAM for Cryogenic Computing

Downloads

Next from DRC 2022

Impact of Corner Rounding on Quantum Confinement in GAA Nanosheet FETs for Advanced Technology Nodes

Similar lecture

Scalable All-Evaporation Fabrication of Efficient Light-Emitting Diodes with Hybrid 2D–3D Perovskite Nanostructures

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES