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Traditionally, data is labelled by those willing to do the work. This can lead to large amounts of available training samples, but often falls short as popular models can take tens of thousands of labelled data points to train. With active learning, the burden of labelling is minimized. The human provides targeted answers to decrease uncertainty in the model. With the human and model working together, labelling automation through prediction is enabled. 

NAML 2022

Active Learning: Super Charge Data Labelling

Naval Information Warfare Center Pacific is partnering with AFCEA San Diego chapter to host the workshop.

The NAML workshop is an opportunity for researchers from Navy research and development centers and our partner organizations to exchange technical ideas and to come together as a team.

The goals of NAML are:

* To spread awareness of current machine learning research relevant to Naval applications

* To connect machine learning researchers with experts in military requirements

* To build and strengthen collaborations within the defense research community

**Watch this video to hear about the AFCEA purpose.**

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NAML 2021

poster

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Naval Information Warfare Center Pacific is partnering with AFCEA San Diego chapter to host the workshop.

The NAML workshop is an opportunity for researchers from Navy research and development centers and our partner organizations to exchange technical ideas and to come together as a team.

The goals of NAML are:

To spread awareness of current machine learning research relevant to Naval applications

To connect machine learning researchers with experts in military requirements

To build and strengthen collaborations within the defense research community


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</figure>

Naval Information Warfare Center Pacific is partnering with AFCEA San Diego chapter to host the workshop. The NAML workshop is an opportunity for researchers from Navy research and development centers and our partner organizations to exchange technical ideas and to come together as a team.

The goals of NAML are:

To spread awareness of current machine learning research relevant to Naval applications

To connect machine learning researchers with experts in military requirements

To build and strengthen collaborations within the defense research community



DARPA’s Real Time Machine Learning (RTML) program seeks to reduce the design costs associated with developing ASICs tailored for emerging ML applications by developing a means of automatically generating novel chip designs based on ML frameworks. The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler’s capabilities across two critical, high-bandwidth application areas: 5G networks and image processing.

Real Time Machine Learning: Automated Flows Enabling Concept to Chip

VeriGOOD-ML is an automated methodology for generating machine learning (ML) hardware for DNN and non-DNN ML algorithms. The VeriGOOD-ML generator takes as input a high-level description of an ML algorithm in a standard format such as ONNX, and outputs Verilog RTL code, with no human in the loop. The Verilog RTL is then translated through a back-end design flow to GDSII, driven by a design planning approach that is well tailored to the macro-intensive nature of ML platforms. VeriGOOD-ML uses three approaches to build ML hardware: (1) the TABLA platform uses a dataflow architecture that is well suited to non-DNN ML algorithms; (2) the GeneSys platform, with a systolic array and a SIMD array, is optimized for implementing DNNs; and (3) the Axiline approach synthesizes small ML algorithms by hardcoding the structure of the algorithm into hardware, thus trading off flexibility for performance and power.

The Verilog generator is complemented by an approach that performs design space exploration of the configurations of each hardware engine to determine the best implementation of the hardware. The performance metrics of the implemented hardware are significantly affected by the configuration of the hardware platform and the physical implementation from RTL to GDS. Key metrics include the power, performance, and area (PPA) of the hardware engine, and the power, execution time, and accuracy of the ML algorithm at the system level. The talk overviews the overall methodology, from architecture to back-end design to hardware implementation, and presents the results of VeriGOOD-ML on a set of ML benchmarks.

Physically-aware Automated ML Hardware Generation using VeriGOOD-ML

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements.
However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages.
Agile hardware design tools based on compiler techniques, instead, can quickly produce an application specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description.
We present the SODA Synthesizer, a modular and opensource hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multi-level representations to progressively lower and optimize the input code.
Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 GFLOPS/W (32-bit precision) efficiency on typical convolutional neural network operators.

Bridging Python to Silicon smartly: the SODA toolchain

Using Apache TVM for automated end-to-end HW/SW co-design for deep learning.

Using Apache TVM for End-to-end HW/SW Co-design

Ransomware is a rising threat that utilizes malicious software that prevents a user from accessing computer files, systems, or networks demanding a ransom for their return. This poster introduces a novel technique to measure the impact of a ransomware attack. Specifically, factors such as the ransom paid, recovery time or duration, and critical infrastructure targeted, are used to define the impact of an attack. To this end, a dataset of 980 ransomware attacks worldwide from October 2013 to June 2021 is analyzed and a general framework is established. The final results show that organizations in the five lifeline critical infrastructures (water, energy, transportation, communication, and information technology) have the largest impact scores. Moreover, this new metric aims at appraising the effectiveness of cybersecurity measures at a given organization.

Measuring the impact of a ransomware attack

Today’s investments in aircraft and Naval Aviation Support Equipment (SE) sustainment lack a coordinated response. Current metric sustainment reports address aircraft or SE top degrader equipment separately. To our knowledge there is no current association on the SE degrader investments that will have the greatest impact on aircraft readiness. This research will allow for the transition of these findings into an integrated metric data product report.

Naval Aviation Support Equipment Impact on Aircraft Readiness

Rapidly advancing fields of software technologies and the development of software autonomy frameworks present new opportunities and challenges for the DoD. While these technologies allow the DoD to rapidly augment capabilities, integration complexity increases, which oftentimes overwhelms Autonomy Practitioners, or the human end users of autonomy frameworks. This paper describes the utilization of Research and Autonomy Innovation Development Environment and Repository (RAIDER), a Navy maintained repository of autonomy frameworks, intended to leverage the promise of rapid integration while mitigating integration complexity. In particular, RAIDER encourages coordination of acquisition efforts through the reuse and repurposing of existing products, which ultimately improves system interoperability and frees up resources (e.g. staff, schedule). The acquisition strategy and tools laid out in this paper can be applied to implement new mission capabilities and integrate technologies such as machine learning on existing hardware platforms.

Streamlining Software Acquisition Processes Through the Use of an Autonomy Framework Repository and Environment

We would like to present a use case very relevant to most predictive analytic situations in military data environments where high predictive accuracy is required with less-than-ideal data integrity (limited data availability, missing data, inconsistencies, specialized vocabulary, small training data sets, etc.)

In our presentation we’ll illustrate a proprietary algorithm, Higher Order Low-Resource Learning (HO-LRL™) which is based on a suite of technologies facilitating learning models on both dynamic and static data by transforming data representations into a “higher order” format based on latent relationships between data items. This transformation can be incorporated into a number of data agnostic algorithms providing a significant functional and exponential advantage over currently used algorithms in the NLP field when confronted with limited data on a project. 

Data quality, consistency and integrity remains a common challenge across Artificial Intelligence use cases. This is especially true within Natural Language Processing (NLP). Most algorithms and state of the art machine learning methods rely on large numbers of training examples to provide high accuracy percentages. 

Modeling from a previous predictive analytics project Serco performed for customers in the defense industry, Serco and Intuidex partnered to develop a use case to better address low data environments. The previous project presented various challenges around data quality, integrity, with minimal ability to use Natural Language Processing against unstructured data providing context for generating predictions. 

Our use case replicated these conditions in the lab to test Intuidex’s technology and innovations in algorithms. The data was randomly generated using a similar data profile and only 0.2% of the original data volume provided to compare against various front-runners for this use case. Intuidex technology was able to overcome the roadblocks previously experienced through data cleansing, validation, utilization of innovative algorithms such as high order learning and low-resource learning, predictive analytics, and pattern of life modeling. 

In our use case we compared the HO-LRL algorithm with the algorithm from the original NAVSEA implementation custom developed by a team of data scientists, along with standard Stanford NLP GloVe, Facebook AI RoBerta, and Google AI BERT. The largest benefit noted was in the amount of data required to reach a higher accuracy measure which was 0.2% of what was used by the algorithm in the original implementation, along with other competitors. Accuracy and MAPE also improved dramatically by at least 13 precision points over the original and competitors while requiring exponentially less data (180 samples minimum versus 3 million plus used in original use case), training time (<20 seconds), and time to implement the solution (2 weeks). 

Our use case focused on predictive maintenance, but our findings supported related previous work, where it was shown that leveraging higher order dependencies improves the performance of a number of different applications including threat detection in streaming message traffic, anomaly and threat detection in network traffic, classification of radio nuclear signals in border protection, as well as applications in ecommerce, law enforcement, and counterterrorism. 

In conclusion, our use case illustrates how the HO-LRL algorithm provides a significant advantage when confronted with limited data which can be a very common situation on projects in military environments using Natural Language Processing (NLP). 


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Real Time Machine Learning: Automated Flows Enabling Concept to Chip

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