United States

Significant enhancement of hot-carrier degradation and time-dependent dielectric breakdown by mechanical stress was observed in CMOS FETs. Mechanical stress was induced locally in the channels of p- and n-type FETs by applying a vertical load with a diamond tip of a nanoindenter. The induced GPa level stress was calculated with finite element modeling. Mechanical stress induces a piezoresistance effect in both p- and n- channels, leading to an increase in source/drain leakage and drive currents and drastic enhancement of impact ionization. This in turn results in strongly enhanced hot-carrier degradation and hot-electron-induced punch-through effects in pFETs and enhanced hot-carrier degradation and time-dependent dielectric breakdown in nFETs. 

IRPS 2022

Observation of Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress

mechanical stress

hot-carrier degradation

breakdown

technical paper

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A constant current stress scheme is implemented for endurance study on OTS-PCM devices for the first time. It provides a feasible method to estimate the read/write endurance for cross-point PCM products, which can save testing time for chips qualification.          

Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme

Endurance ~ 1012 cycling of ferroelectric (FE) and antiferroelectric (AFE) HfZrO2 (HZO) capacitors are achieved experimentally by adjusting the programming pulse width (tp). The correlation between switching polarization (△P) and fatigue behavior of high endurance is discussed. For long tp (= 1 µs), AFE exhibits excellent endurance with &gt; 1010 cycles as compared with FE ~ 109 cycles. With shortening tP, the endurances of FE and AFE are significantly improved. There is no significant degradation until &gt; 1011 cycling is observed for FE with tp=20ns. 

Correlation between Access Polarization and High Endurance (~ 1012 cycling) of Ferroelectric and Anti-Ferroelectric HfZrO2

Hafnium oxide-based ferroelectric tunnel junctions (FTJs) are novel nonvolatile memory devices with promising advantages such as non-destructive readout in comparison with conventional ferroelectric random access memories. Reliability aspects of FTJ devices need to be investigated, including endurance, retention, ferroelectric switching, breakdown characteristics, and memory window. These characteristics exhibit promising results at room temperature; however, further analysis is required at different operating temperatures. In this work, we demonstrate the FTJ device characteristics at different temperatures varying from -40 °C to 60 °C.

Impact of Temperature on Reliability of MFIS HZO-based Ferroelectric Tunnel Junctions

To enable high-density cross-point arrays of magnetic memory a suitable access device is necessary. A promising candidate for this role is a metal-semiconductor-metal (MSM) tunneling device. In this work, the operation of an ultrathin Pt\6nm a-IGZO\Pt stack as an MSM selector is discussed. The focus is given to understanding the breakdown mechanism at high current regime, which prevents it from reaching the target current density. The breakdown is preceded by a gradual degradation process, which is manifested as an increase in high-field current after prolonged stress. This effect is recoverable – current returns to original value after sufficient delay time. Based on these observations, we propose a mechanism, where increased high-field current can be explained as a decrease in Schottky barrier height arising from stress-induced increase in oxygen vacancies.

Degradation mechanism of amorphous IGZO-based bipolar metal-semiconductor-metal selectors

The self-protection of SOI RF switches is presented in this paper. TLP ESD test results show that the ESD protection performance of SOI RF switches is impacted by various parameters, including switch array gate channel length, finger width, finger number, and RF switch stack number. The physics of the SOI RF switch ESD protection mechanism is also studied by comparing TLP ESD test results from SOI RF switch splits and other ESD protection structures. It is concluded that the SOI RF switch self-protection process during ESD transients contains two mechanisms: NMOS channel conduction triggered by gate coupling effect and parasitic bipolar turning on. 

Characterization and Analysis of RF Switches  in SOI Technology for ESD Protection

In this work, we demonstrate experimentally an RRAM-based IMC logic concept with strong resilience to RRAM variability, even after one million endurance cycles. Our work relies on a generalization of in-memory Scouting Logic, and we demonstrate it experimentally with up to 16 parallel devices, a new milestone for RRAM in-memory logic. Moreover, we combine IMC with a new smart Multi-Level-Cell (MLC) programming algorithm resilient to conductance relaxation and demonstrate experimentally, for the first time, an IMC RRAM-based MLC 2-bit adder.

Experimental demonstration of Single-Level and Multi-Level-Cell RRAM-based In-Memory-Computing with up to 16 parallel operations

Voltage surges induced by electrostatic discharge (ESD) impacts on the backside of an integrated circuit (IC) chip in flip-chip packaging potentially causes reliability problems and even leads to malfunctioning. On-chip voltage waveform monitor circuits on its frontside evaluate the surge as high as 200 mV when ESD gun at 200 V is discharged to the Si substrate backside through the contact resistance of 5 kΩ to the backside of a 350 µm thick Si substrate. The distribution of voltages over the frontside area of an IC chip is measured and explained with full-system level backside ESD simulation. 


Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging

This paper investigates the
characterization of charge trapping and its modelling on hafnia-based
ferroelectric field effect transistors (FeFETs). Defect characterization on
MOSFETs can be done by studying threshold voltage shifts (DVth) as a function of charging and
relaxation times. At positive gate voltages one expects electron trapping in
the gate oxide to result in a positive shift of the threshold voltage (Vth). However, on a FeFET those conditions
will induce polarization changes in the gate oxide leading to a negative Vth-shift, complicating the characterization
of defect levels. We aim to alleviate these difficulties by modelling the
polarization and trapping in FeFETs over a wide range of timescales, suitable
for defect characterization. We demonstrate quantitative agreement on long
timescales with a static polarization model while a time-dependent polarization
model can be used for qualitative agreement over a wide range of times from 30
ms to 2 ks.

Trap-polarization interaction during low-field trap characterization on hafnia-based ferroelectric gatestacks

Integrating CMOS circuits and qubits at cryogenic temperatures a key challenge to enable up-scaling of quantum computers. One approach to reduce power consumption is to optimize designs towards operation at lower supply voltages. However, this reduces the tolerable margins on variability and device to device variations. In this study, we present the time-zero variability and mismatch of nMOS transistors from room temperature down to 4K. We investigate the physical origins of variability at cryogenic temperatures. We estimate the influence of different on-current variability sources and observe that another source of mismatch, likely contact resistance, becomes dominant at low temperatures.

Temperature Dependent Mismatch and Variability in a Cryo-CMOS Array with 30k Transistors

While LDMOS is one of the most widely used power transistors it has persistent reliability issues (e.g., HCD), because of the high applied bias.  Several efforts have been made to model HCD in TCAD. However, the lack of a feasible experimental approach to extract in LDMOS, made it challenging to verify the  obtained from TCAD. Here, we demonstrate the capability of the S2PCP technique to extract,  quantify the spatial and temporal evolution, identify the differences between experimental and TCAD and suggest possible physical mechanisms responsible. This analysis establishes robustness and identifies the limitations of TCAD modeling. 

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Observation of Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress

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Endurance Evaluation on OTS-PCM Device using Constant Current Stress Scheme

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