United States

Power device characteristics are affected by X-rays used during the inspection of power modules. In this study, the effects of materials and structures of power MOSFETs on the overall degradation were analyzed by irradiating Si MOSFETs and SiC MOSFETs with X-rays using a commercial inspection system. In addition, the effectiveness of thermal and gate voltage annealing was investigated for the irradiated devices. The experimental results confirmed the high radiation tolerance of SiC MOSFETs. In addition, the irradiated devices exhibited difficulty in recovering the shifted threshold voltage without compromising the reliability of the device, indicating that the effects of degradation persisted for a long time.

IRPS 2022

Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Its Recovery

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Threshold voltage instability in 4H-SiC MOSFETs was investigated by means of combined cyclic gate bias stress measurements and single gate bias point measurements. This allowed to separate the contributions of interface states (Nit) and near interface oxide traps (NIOTs) in the nitridated deposited gate oxides. Nanoscale chemical analyses by electron energy loss spectroscopy allowed to correlate these trapping states to the presence of a sub-stoichiometric silicon oxide (~1 nm) and carbon-related defects (&lt;1 nm) on different SiO2/4H-SiC interfaces In particular, the sub-stoichiometric silicon oxide was correlated to the interface states and the carbon-related defects have been correlated to the NIOTs.

SiO2/4H-SiC interfacial chemistry as origin of the threshold voltage instability in power MOSFETs

The circuit functionalities of Complementary Metal-Oxide-Semiconductor (CMOS) devices on 4H-SiC for digital and analog circuit applications beyond 200˚C have been extensively studied, however, the reliability of the devices on SiC needs to be demonstrated due to the traps at/near the dielectric interface. In this report, the reliability of n- and p- Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) has been studied on three different gate oxide conditions – thick thermally grown, ultrathin thermal + thick CVD oxide and ultrathin thermal + thin CVD oxide in terms of their bias temperature instability (BTI) measurement. The MOSFETs were stressed at various constant bias voltages at 150˚C and up to 105s. The threshold voltage shift due to positive bias on n-MOSFET is &lt;0.5V after 105s at +25Vwhile p-MOSFET shows a larger shift of -1.9V shift after 105s at -25V and 150˚C for ultrathin + thick CVD oxide. The report also establishes improvement in reliability of p-MOSFETs with ultrathin + CVD oxides over thermally grown oxides.

Bias Temperature Instability on SiC n- and p-Channel MOSFETs for High Temperature CMOS Applications

In-memory computing (IMC) with memory arrays allows reducing the time and energy consumption for matrix vector multiplication (MVM) for artificial neural networks (ANN) inference. However, the IMC accuracy is affected by nonidealities, such as program/read variations of device conductance and the parasitic voltage (IR) drop along the wires, whose impact quickly increases when increasing the array size. This work presents new IMC circuit architectures for mitigating both variations and IR drop at the same time. The  new schemes allow for improving the accuracy of an ANN from 72.7% to 94.9%, compared to a software accuracy of 96.9%, at the expense of an increase of the memory array area.

Mitigating read-program variation and IR drop by circuit architecture in RRAM-based neural network accelerators

Resistive-switching random access memory (RRAM) is a promising technology for in-memory computing (IMC) to accelerate training and inference of deep neural networks (DNNs). This work presents the first physics-based statistical model describing (i) multilevel RRAM device program/verify (PV) algorithms by controlled set transition, (ii) the stochastic cycle-to-cycle (C2C) and device-to-device (D2D) variations within the array, and (iii) the impact of such imprecisions on the accuracy of DNN accelerators. The model can handle the full chain from RRAM materials/device parameters to the DNN performance, thus providing a valuable tool for device/circuit codesign of hardware DNN accelerators.

Statistical model of program/verify algorithms in resistive-switching memories for in-memory neural network accelerators

In this paper, we present a detailed study of negative bias temperature instability (NBTI) and Time dependent dielectric breakdown (TDDB) reliability in p-type stacked gate- all -around (GAA) Nanosheet (NS) transistors with SiGe channel and compared with NS Si pFETs. Robust NBTI and TDDB reliability performance is achieved on SiGe gate-all-around NS.


SiGe Gate-All-around Nanosheet Reliability

The issues related to the failure analysis of 4H-SiC PowerMOSFET failed at EWS (Electrical Wafer Sorting) such as the channel leakage current is investigated. In particular, EWS is carried out in the namely defect free wafers areas monitored at several inline levels. This paper reports on the electrical based methods used to spot macroscopic defects even if they are invisible at optical wafer inspections. In particular, the current separation technique on source and gate terminals allowed to reduce the number of  candidate samples to be investigated

Failure analysis addressing method of optically undetected defectivity on 4H-SiC PowerMOSFET epitaxial layer

This work presents the influence of SiC epitaxial wafer quality on yield of SiC-DMOSFETs. Various wafer quality indicators were estimated by an integrated wafer quality evaluation system. SiC-DMOSFETs were fabricated on six 100 mm 4H-SiC epitaxial wafers. We show that the yield of SiC-DMOSFETs is related to threading screw dislocation density, defect density and bunched-steps length density evaluated by wafer inspection apparatuses.

Influence of SiC epitaxial wafer quality on yield of 1.2kV SiC-DMOSFETs

Several designs of 1.2kV-rated 4H-SiC PiN diodes and Junction Barrier Schottky (JBS) diodes have been successfully fabricated with various P+ implantation conditions resulting in different junction profiles. P+ regions were implanted at both room temperature and elevated temperature in order to monitor the generation of Basal Plane Dislocations (BPDs) and study their impact on device long term reliability. It was found that, when the dose in the deeper portion of the junction (implemented by high energy) is well suppressed, static and long-term reliability performances of room temperature implanted devices can be maintained similar to those of high temperature implanted devices.

Static Performance and Reliability of 4H-SiC Diodes with P+ Regions Formed by Various Profiles and Temperatures

Resistive random-access memory (RRAM)-based in-memory computing (IMC) recently became a promising paradigm for efficient deep neural network acceleration. The multi-bit RRAM arrays provide dense storage and high throughput, whereas the physical non-ideality of the RRAM devices impairs the retention characteristics of the resistive cells, leading to accuracy degradation. On the algorithm side, various hardware-aware compression algorithms have been proposed to accelerate the computation of deep neural networks (DNNs) computation. However, most recent works individually consider the "model compression" and "hardware robustness". The impact of the RRAM non-ideality for the sparse model is still under-explored. In this work, we present a novel temperature-resilient RRAM-based IMC scheme for reliable DNN inference hardware. Based on the measurement from a 90nm RRAM prototype chip, we first explore the robustness of the sparse model under the different operating temperatures (25°Cto 85°C). On top of that, we propose a novel robustness-aware pruning algorithm, then further enhance the model robustness with a novel sparsity-aware noise-injected fine-tuning. The proposed scheme achieves &gt;92% CIFAR-10 inference accuracy after one-day operation, which is &gt;37% higher than the state-of-art method.

Sparse and Robust RRAM-based Efficient In-memory Computing for DNN Inference

The advent of Artificial Intelligence (AI) and big data era brought an unprecedented (and ever growing) need for fast and energy efficient computation that cannot be obtained with the classical von Neumann computing architecture. This paved the way to new technologies that try to mimic the human brain to leverage its energy efficient and distributed computing. Non-volatile memory technologies seem to be the ideal solution for the hardware implementation of artificial neurons and synapses of Neural Network (NN) architectures and have been extensively investigated in the last years. However, they often suffer from limited linearity and symmetry, poor retention, and high variability, thus requiring significant advancements for their mass adoption in NNs. One of the cornerstones on which the required efforts must be based is certainly represented by device simulations, which can be effectively used to achieve a full understanding of the physics governing the device, which in turn is a pre-requisite for their design, optimization and successful exploitation in neuromorphic applications. In this scenario, we focus on Transition Metal Oxide (TMO)-based RRAM, Ferroelectric Tunnel Junctions (FTJ) and 3D-NAND Charge Trap devices and use simulations to address key issues related to neuromorphic operation (linearity and asymmetry) and reliability (variability and retention).  

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Characteristic Degradation of Power MOSFETs by X-Ray Irradiation and Its Recovery

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SiO2/4H-SiC interfacial chemistry as origin of the threshold voltage instability in power MOSFETs

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