United States

The single event induced crosstalk of monolithic 3D (M3D) integrated inverter chain is investigated using GEANT4 and TCAD simulations from layout, spacing, length, supply voltage and transistor size. The accurate ionization profiles are initially obtained and modelled in TCAD. Meanwhile, the crosstalk capacitances between interconnect lines or transistors are acquired through 3D simulation. Results show that the crosstalk pulse is closely related to interconnect length and peaks at 50 µm for transistor-level M3D. Vertical alignment of PMOS and NMOS in two inverter chains (gate level) respectively on different tier is the optimal layout to mitigate the single event induced crosstalk pulse (5.9 ps and 130 mV). In addition, increasing thickness of inter-layer dielectric is the best way to eliminate the crosstalk effect nearly without area penalty, which is the intrinsic advantage compared to planar circuits. 

IRPS 2022

Single event induced crosstalk in monolithic 3D CMOS integrated circuits based on 22 nm FD-SOI

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IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The self-protection of SOI RF switches is presented in this paper. TLP ESD test results show that the ESD protection performance of SOI RF switches is impacted by various parameters, including switch array gate channel length, finger width, finger number, and RF switch stack number. The physics of the SOI RF switch ESD protection mechanism is also studied by comparing TLP ESD test results from SOI RF switch splits and other ESD protection structures. It is concluded that the SOI RF switch self-protection process during ESD transients contains two mechanisms: NMOS channel conduction triggered by gate coupling effect and parasitic bipolar turning on. 

Characterization and Analysis of RF Switches  in SOI Technology for ESD Protection

In this work an implicit finite element model of a Printed Circuit Board (PCB), connectors, and stiffener is developed. The effect of several parameters on the strain distribution on the board was analyzed. The PCB was bolted to an aluminum stiffener. The simulation went through several steps to consider the effect of the solder reflow process as well as bolt pretension forces and plug-in forces of the connectors. Based on the simulation, board warpage and bolt pretension forces had significant effect on board strain. 

Numerical Simulation and characterization of PCB Warpage

Voltage surges induced by electrostatic discharge (ESD) impacts on the backside of an integrated circuit (IC) chip in flip-chip packaging potentially causes reliability problems and even leads to malfunctioning. On-chip voltage waveform monitor circuits on its frontside evaluate the surge as high as 200 mV when ESD gun at 200 V is discharged to the Si substrate backside through the contact resistance of 5 kΩ to the backside of a 350 µm thick Si substrate. The distribution of voltages over the frontside area of an IC chip is measured and explained with full-system level backside ESD simulation. 


Voltage Surges by Backside ESD Impacts on IC Chip in Flip Chip Packaging

In this paper, a high holding voltage dual-directional silicon-controlled rectifier (SCR) with an embedded shunt path (HVDDSCR-ESP) for high-voltage I/O electrostatic discharge (ESD) protection is proposed. Based on the 0.13-μm BCD process, multi-current pulses that mimic the transmission line pulse (TLP) are applied to devices by using Sentaurus-TCAD. The results reveal that the proposed structure, compared with the conventional low-trigger dual directional SCR (LTDDSCR), has adjustable high holding voltage and good ESD robustness. In addition, the working mechanisms are also investigated, and the proposed device as the ESD cell is beneficial for the 12V applications and has no risk of latch-up.

A Novel Latch-Up-Immune DDSCR Used for 12 V Applications

Adhesion-Limit in Refractory Transition Metal (Mo) Contact Relay Operation at 300 °C— Avoiding Overestimation for Modern ICs

Adhesion-Limit in Refractory Transition Metal (Mo) Contact Relay Operation at 300 °C— Avoiding Implicated Overestimation for Modern ICs

While LDMOS is one of the most widely used power transistors it has persistent reliability issues (e.g., HCD), because of the high applied bias.  Several efforts have been made to model HCD in TCAD. However, the lack of a feasible experimental approach to extract in LDMOS, made it challenging to verify the  obtained from TCAD. Here, we demonstrate the capability of the S2PCP technique to extract,  quantify the spatial and temporal evolution, identify the differences between experimental and TCAD and suggest possible physical mechanisms responsible. This analysis establishes robustness and identifies the limitations of TCAD modeling. 

A Critical Examination of the TCAD Modeling of Hot Carrier Degradation for LDMOS Transistors

Significant enhancement of hot-carrier degradation and time-dependent dielectric breakdown by mechanical stress was observed in CMOS FETs. Mechanical stress was induced locally in the channels of p- and n-type FETs by applying a vertical load with a diamond tip of a nanoindenter. The induced GPa level stress was calculated with finite element modeling. Mechanical stress induces a piezoresistance effect in both p- and n- channels, leading to an increase in source/drain leakage and drive currents and drastic enhancement of impact ionization. This in turn results in strongly enhanced hot-carrier degradation and hot-electron-induced punch-through effects in pFETs and enhanced hot-carrier degradation and time-dependent dielectric breakdown in nFETs. 

Observation of Significant Enhancement of HCD and TDDB in CMOS FETs by Mechanical Stress

Hot electron trapping can significantly impact the performance of GaN-based HEMTs. Within this paper, the effect of current density and electric field on the severity of hot-electron degradation is presented. The experiments demonstrate that: (i) we can isolate the hot electron trapping processes, (ii) the hot-electron induced performance degradation follows a logarithmic kinetic, which can be modeled by rate equations, and (iii) the amount of current collapse has a linear dependence on the applied electric field and a logarithmic dependence on the current density, in agreement with theoretical equations.

Hot-Electron trapping in GaN-based HEMTs

A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type gate under pulse stress conditions. Results show that the time-dependent gate breakdown (TDGB) can be determined by two factors: i) the total ON-time during which the device is subjected to a positive gate bias before the failure; ii) the number of pulses, hence the number of switching phases from OFF- to ON-State and vice versa. The severity of the degradation ascribed to transition phases depends on the OFF-time (tOFF) and transition time (tTR = tRISE = tFALL). In particular, the shorter tOFFand tTR, the higher the Schottky junction voltage drop and the current peak during the switching phase, respectively. The higher voltage drop is ascribed to the semi-floating potential of the p-GaN layer. 

Gate Reliability of p-GaN Power HEMTs Under Pulsed Stress Condition

Using a full quantum mechanical calculation, we investigate the fundamental validity of the Schottky emission model for its applications to electron injection in dielectrics from a metal or semiconductor electrode. We cover a wide range of electric fields from10kV/cm to 10MV/cm and temperatures for a large range of barrier heights. We conclude the Schottky emission model is only applicable for a very small class of dielectrics under 0.1MV/cm and at high temperatures over ~330°K.  For many defective dielectrics such as BEOL/MOL and MIMCAP dielectrics with a barrier height (FB ≥ 1eV), its conduction is negligible for electric fields larger than 0.1MV/cm while thermionic-field or field emission becomes dominant. If Schottky emission process is indeed valid, then the FN tunneling current must be smaller than that of the Schottky emission process with the same FB. Several misconceptions and malpractices as widely occurred in the dielectric community have been clarified. This work carries significant impact on BEOL Breakdown model development

Quantum Mechanical Connection of Schottky Emission Mechanism and Its implications on Breakdown Methodology and Conduction Modeling for BEOL Low-k Dielectrics

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Single event induced crosstalk in monolithic 3D CMOS integrated circuits based on 22 nm FD-SOI

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Characterization and Analysis of RF Switches in SOI Technology for ESD Protection

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