France

In this presentation we discuss the design, implementation and measurements of Tb/s/channel optical communication circuits realized in III-V Lab InP DHBT process. Realizations using InGaAs- and GaAsSb-base devices will be presented and compared, from transistor to circuit performances.
The design flow is detailed with specific focus on key trade-offs to reach &gt;3-4 Vpp output swings conjugated with &gt;100 GHz analog bandwidth as well as circuits’ design for electro-optical systems with new transmission formats using innovative DSP algorithms allowing higher transmission rates and increased spectral efficiency, like m-ary pulse-amplitude modulation (m-PAM) or quadrature amplitude modulation (m-QAM) formats. We also present the design and measurements of digital multiplexing selector operation at record 212-GBd speed and its system implementation for intra data-center communications.


ESSCIRC ESSDERC Educational Events

Recent advances in high-speed and large-swing integrated circuits implemented in InGaAs and GaAsSb InP DHBT for terabit-class optical communications

terabit optical systems (tb/s)

double heterojunction bipolar

indium phosphide (inp)

llinear e/o modulator driver

analog multiplexer (amux)

pulse mplitude modulation (pam)

large-swing analog circuits

high-speed integrated cicruits (ic)

digital-to-analog converter (dac)

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





In this presentation we discuss the design, implementation and measurements of Tb/s/channel optical communication circuits realized in III-V Lab InP DHBT process. Realizations using InGaAs- and GaAsSb-base devices will be presented and compared, from transistor to circuit performances.
The design flow is detailed with specific focus on key trade-offs to reach >3-4 Vpp output swings conjugated with >100 GHz analog bandwidth as well as circuits’ design for electro-optical systems with new transmission formats using innovative DSP algorithms allowing higher transmission rates and increased spectral efficiency, like m-ary pulse-amplitude modulation (m-PAM) or quadrature amplitude modulation (m-QAM) formats. We also present the design and measurements of digital multiplexing selector operation at record 212-GBd speed and its system implementation for intra data-center communications.


technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

Some Insights in Automated Netlist Reverse Engineering

System-on-Chip platforms have been increasingly extended with trusted computing functionality to provide strong protection for sensitive software applications through enclaves that only require trust in the hardware and minimal software components. However, the deployed enclave architectures are still suffering from various shortcomings such as the lack of secure I/O, or being vulnerable to side-channel attacks. Thus, recent research works propose new enclave architectures with more comprehensive threat models and advanced security features. A majority of these solutions is being developed on the open RISC-V architecture. In this paper, we present a brief overview of the RISC-V-based enclave architectures, discuss their features, limitations and open challenges.

In Hardware We Trust? From TPM to Enclave Computing on RISC-V

Electro Magnetic (EM) attacks: passive side-channel and active fault attacks

InP DHBTs are well known for their capability to provide both high cutoff frequencies together with high breakdown voltage. III-V Lab has developed for several years very high-speed and high swing integrated circuits based on this technology. In this presentation, we will focus on the technological features of present 0.7-μm InP/GaInAs DHBT exhibiting around 400-GHz fT and fMAX, as well as a breakdown voltage above 4.5 V and a high dissipated power above 35 mW at peak fT. The relaxed emitter width enables to work at moderate current densities and ensure a very high fabrication yield and performance homogeneity on 3’’ wafer. More compact 0.5-µm DHBT and circuit oriented device generation allowing above 500 GHz fmax is also presented. We will demonstrate that our technology is also compatible with the fabrication of GaAsSb-based InP DHBT and a comparison of the key figures of merits between Type-I and Type-II InP DHBTs fabricated in a same process will be presented.

InP DHBT technology at III-V Lab

InP DHBT technologies are well established for high data rates at the III-V Lab in France and as a foundry at Teledyne in US. FBH has developed over the past years three InP DHBT technologies for high performance communications and sensing applications, with particular view on signal generation and amplification, as well as signal conversion. This presentation will provide details on the achieved results in the three InP DHBT technologies at FBH. The most prominent technology is the transferred substrate (TS) InP DHBT technology at FBH, where the host InP substrate is removed and the MMIC is realized on an eligible substrate of choice. With this technology, FBH has achieved 530 GHz cut-off frequency with a breakdown voltage of > 4 V. Using the TS InP DHBT process FBH has developed an InP-on-BiCMOS process, which is unique worldwide and which combines the advantages of high complexity of SiGe BiCMOS circuits with the performance capabilities of InP technology. Signal generation with integrated PLL synthesis has been demonstrated with this technology up to 300 GHz. Also highly compact front-end circuits for radar applications have been published. More recently, FBH has developed a robust triple-mesa MMIC process based on InP DHBT devices with cut-off frequencies beyond 300 GHz. The advantages and challenges of all three process will be discussed and evaluated during the talk

InP DHBT technologies at FBH

“Type-II” InP/GaAsSb/InP Double Heterostructure Bipolar Transistors (DHBTs) with maximum oscillation frequencies fMAX = 1 THz will be described.

The transistors use a 20-nm-thick composition- and impurity- graded GaAsSb base and a 125-nm thick Si-doped InP collector. The THz fMAX figure-of-merit is achieved by optimizing lateral scaling: the emitter width is 150 nm and the base contact is undercut down to 50 nm to match the base contact electrical transfer length. The (0.15 × 7.5) µm2 devices feature a maximum DC current gain β = 14 and a common emitter breakdown voltage BVCEO = 5.05 V. Performance figures-of-merit will be contrasted across technologies –as it turns out, InP/GaAsSb DHBTs offer advantages in efficiency, linearity and noise that combine favorably for a variety or analog and digital circuits.

The influence of self-heating on output power properties in 94 GHz load-pull will be discussed, highlighting the importance of thermal management in achieving ultimate device performance.

Current work is under way toward a new process architecture: first results will be shown if devices can be successfully implemented.

THz InP/GaAsSb DHBTs

A multiscale TCAD model is introduced in the presentation to investigate the intrinsic physical properties of type-II DHBTs. The simulation environment is composed of a two-dimensional hydrodynamic model and an one-dimensional full-band atomistic quantum transport solver. After careful calibration, good agreements between simulations and experiments have been obtained in both the DC and AC characteristics. Moreover, the transport properties of the device have been investigated in the ballistic and dissipative case. Last but not least, the performance of agreesively down-scaled transistors has been simulated to shed light on the realization of transistors towards and beyond 1 THz.

Multi-Scale Modeling of Type-II DHBTs: from Bandstructure to Self-Heating Effects

While InP heterojunction bipolar transistor technologies show continuous improvement in terms of RF performances, the accurate characterization of these THz transistors is crucial to assess the cut-off frequencies as well as to precisely extract and validate the device compact model, thus enabling millimeter and sub-millimeter-wave IC design. On-wafer measurements are particularly difficult beyond 110 GHz since unwanted parasitic effects become predominant and may mask the intrinsic behavior of the nanoscale device. A such high frequencies, two strategies may be adopted and combined in order to perform accurate on-wafer device measurements at submillimeter-wave frequencies: i) optimizing the test structures’ design in order to minimize the parasitics, ii) developping on-wafer calibration standards on the same substrate as the device to characterize. Coupled with electromagnetic simulation for the test structures design optimization and the measurement's validation, these strategies proved to be efficient for the characterization of InP passive devices up to 500 GHz and InP DHBT up to 330 GHz.

On-Wafer TRL Calibration Kit Design for InP Technologies Characterization Up To 500 GHz

To meet the prerequisites of monolithic indium phosphide based integrated terahertz (THz) technologies that are capable of achieving beyond-5G wireless communications system, a single computationally efficient circuit design tool is essential. Through the implementation of accurate and SPICE-compatible compact models and development of associated process design kits (PDK) for InP double heterojunction bipolar transistors (DHBTs), we demonstrate that next generations of cutting-edge high speed electronic systems will benefit from (i) dedicated parameter extraction procedure,(ii) validation of model parameter set against on-wafer high-frequency measurements and deembedding methods using dedicated test structures in the beyond 110 GHz range,(iii) extrapolation of key figures of merits to scaled device dimensions leveraging a scalable model card.

For the parameter extraction procedure, we investigate the bias, temperature, and frequency dependence of two III-V double heterojunction bipolar transistors technologies based on InGaAs/InP and GaAsSb/InP processes, using a HiCuM/L2 compact model-based multi-geometry scalable parameter extraction methodology. Very good agreement between the model simulations and experimental data is demonstrated. Transistor currents and junction capacitances show very good scaling, thereby allowing the separation of intrinsic and peripheral effects. 

Since thermal management is more critical in III-V technologies compared to Si-based ones, especially from the reliability point of view, for a more accurate description of electrothermal effects in InP HBTs, a new scalable model for the thermal impedance of III-V DHBTs that has been developed based on the physics of heat diffusion within the HBT architecture. The heat flow through both the emitter metal layers and toward the substrate are taken into account for the model development. The model constitutes of individual thermal contributions of the different regions of the intrinsic device and metal layers. On-wafer low-frequency S-parameters measurements have been performed on several device geometries to study the device dynamic self-heating. The model has been validated against the measurements showing good accuracy and scalability. Time-domain pulse measurements have also been performed to correlate with the frequency domain S-parameter measurements. Moreover, accuracy of the scalable model card has been validated against measurements up to 330 GHz on the InP DHBTs leveraging on-wafer measurements on passive devices (open/short) up to 500 GHz, achieved through TRL calibration and E-M simulation of designed test-structures. Finally, prediction of future III-V HBT technologies figures-of-merit for scaled device dimensions of a state-of-the-art InP DHBT is performed by using the generated scalable model card.

Compact Modeling and Parameter Extraction Strategies for InP Double Heterojunction Bipolar Transistors

The paper presents briefly the software used in the Ultimate projet for HiCuM/L2 compact model scalable parameter extraction. The video explains the software functionnalities and the basic theory beyond scalable physics based compact model parameter extraction. An example is given for junction capacitances with a demo of the software operation.

Recent advances in high-speed and large-swing integrated circuits implemented in InGaAs and GaAsSb InP DHBT for terabit-class optical communications

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Recent advances in high-speed and large-swing integrated circuits implemented in InGaAs and GaAsSb InP DHBT for terabit-class optical communications

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Some Insights in Automated Netlist Reverse Engineering

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A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 Up to 1GHz Using Constant-Activity Element Switching

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