France

A multiscale TCAD model is introduced in the presentation to investigate the intrinsic physical properties of type-II DHBTs. The simulation environment is composed of a two-dimensional hydrodynamic model and an one-dimensional full-band atomistic quantum transport solver. After careful calibration, good agreements between simulations and experiments have been obtained in both the DC and AC characteristics. Moreover, the transport properties of the device have been investigated in the ballistic and dissipative case. Last but not least, the performance of agreesively down-scaled transistors has been simulated to shed light on the realization of transistors towards and beyond 1 THz.

ESSCIRC ESSDERC Educational Events

Multi-Scale Modeling of Type-II DHBTs: from Bandstructure to Self-Heating Effects

iii-v material

dhbt

tcad modeling

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

And overview of what security means for ST products, the resulting embedded-security R&D themes, key considerations when doing hardware-security-design for high-volume quality manufacturing, and a short overview of other important emerging embedded security challenges.

Embedded security: A silicon provider's perpective

In this talk, we present state-of-the-art attack and defense methodologies that are based upon machine learning and hardware systems. In particular, we present three works, (i) ProFlip, (ii) HASHTAG and (iii) GenUnluck. (i) ProFlip is the first targeted Data Poisoning/Model Trojan attack framework that can divert the prediction of the DNN to the target class by progressively identifying and flipping a small set of bits in the model parameters. (ii) HASHTAG is the first framework that enables high-accuracy detection of fault-injection attacks on Deep Neural Networks (DNNs) with provable bounds on detection performance. (iii) GenUnluck is the first efficient framework, based upon Genetic Algorithms and AI, that has been shown to break several contemporary logic locking algorithms.

Attacks and Defenses rooted in Machine Learning and Hardware Systems

Side-Channel-Attack Tolerant Crypto Engines

This tutorial presentation overviews power side-channel leakages and attacks on integrated circuit chips featuring cryptographic cores. The knowledge are linked among on-board electromagetic measurements, on-chip voltage monitoring, and full-system level power noise simulation techniques for the in-depth understanding of power side-channel leakage problems.

Side-channel Leakages, Attacks and Simulation for Hardware Security

Some Insights in Automated Netlist Reverse Engineering

System-on-Chip platforms have been increasingly extended with trusted computing functionality to provide strong protection for sensitive software applications through enclaves that only require trust in the hardware and minimal software components. However, the deployed enclave architectures are still suffering from various shortcomings such as the lack of secure I/O, or being vulnerable to side-channel attacks. Thus, recent research works propose new enclave architectures with more comprehensive threat models and advanced security features. A majority of these solutions is being developed on the open RISC-V architecture. In this paper, we present a brief overview of the RISC-V-based enclave architectures, discuss their features, limitations and open challenges.

In Hardware We Trust? From TPM to Enclave Computing on RISC-V

Electro Magnetic (EM) attacks: passive side-channel and active fault attacks

InP DHBTs are well known for their capability to provide both high cutoff frequencies together with high breakdown voltage. III-V Lab has developed for several years very high-speed and high swing integrated circuits based on this technology. In this presentation, we will focus on the technological features of present 0.7-μm InP/GaInAs DHBT exhibiting around 400-GHz fT and fMAX, as well as a breakdown voltage above 4.5 V and a high dissipated power above 35 mW at peak fT. The relaxed emitter width enables to work at moderate current densities and ensure a very high fabrication yield and performance homogeneity on 3’’ wafer. More compact 0.5-µm DHBT and circuit oriented device generation allowing above 500 GHz fmax is also presented. We will demonstrate that our technology is also compatible with the fabrication of GaAsSb-based InP DHBT and a comparison of the key figures of merits between Type-I and Type-II InP DHBTs fabricated in a same process will be presented.

InP DHBT technology at III-V Lab

InP DHBT technologies are well established for high data rates at the III-V Lab in France and as a foundry at Teledyne in US. FBH has developed over the past years three InP DHBT technologies for high performance communications and sensing applications, with particular view on signal generation and amplification, as well as signal conversion. This presentation will provide details on the achieved results in the three InP DHBT technologies at FBH. The most prominent technology is the transferred substrate (TS) InP DHBT technology at FBH, where the host InP substrate is removed and the MMIC is realized on an eligible substrate of choice. With this technology, FBH has achieved 530 GHz cut-off frequency with a breakdown voltage of > 4 V. Using the TS InP DHBT process FBH has developed an InP-on-BiCMOS process, which is unique worldwide and which combines the advantages of high complexity of SiGe BiCMOS circuits with the performance capabilities of InP technology. Signal generation with integrated PLL synthesis has been demonstrated with this technology up to 300 GHz. Also highly compact front-end circuits for radar applications have been published. More recently, FBH has developed a robust triple-mesa MMIC process based on InP DHBT devices with cut-off frequencies beyond 300 GHz. The advantages and challenges of all three process will be discussed and evaluated during the talk

InP DHBT technologies at FBH

“Type-II” InP/GaAsSb/InP Double Heterostructure Bipolar Transistors (DHBTs) with maximum oscillation frequencies fMAX = 1 THz will be described.

The transistors use a 20-nm-thick composition- and impurity- graded GaAsSb base and a 125-nm thick Si-doped InP collector. The THz fMAX figure-of-merit is achieved by optimizing lateral scaling: the emitter width is 150 nm and the base contact is undercut down to 50 nm to match the base contact electrical transfer length. The (0.15 × 7.5) µm2 devices feature a maximum DC current gain β = 14 and a common emitter breakdown voltage BVCEO = 5.05 V. Performance figures-of-merit will be contrasted across technologies –as it turns out, InP/GaAsSb DHBTs offer advantages in efficiency, linearity and noise that combine favorably for a variety or analog and digital circuits.

The influence of self-heating on output power properties in 94 GHz load-pull will be discussed, highlighting the importance of thermal management in achieving ultimate device performance.

Current work is under way toward a new process architecture: first results will be shown if devices can be successfully implemented.

Multi-Scale Modeling of Type-II DHBTs: from Bandstructure to Self-Heating Effects

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Multi-Scale Modeling of Type-II DHBTs: from Bandstructure to Self-Heating Effects

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Next from ESSCIRC ESSDERC Educational Events

Embedded security: A silicon provider's perpective

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Characterization and TCAD Modeling of Mixed-Mode Stress Induced by Impact Ionization in Scaled SiGe HBTs

Stay up to date with the latest Underline news!

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RESOURCES

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