France

Recent work has shown that architectural isolation can be violated through software side channel attacks that exploit microarchitectural performance optimizations such as speculation to leak secrets. While turning off microarchitectural optimizations can preclude some classes of attacks, we argue that performance and security do not have be in conflict, provided processors are designed with security in mind.

We advocate designing processors to support enclaves, which are processes with an associated security policy, and espouse a principled hardware/software co-design approach to eliminating entire attack surfaces relevant to the security policy through microarchitectural isolation, rather than plugging attack-specific privacy leaks. As a case study of this approach, we describe both in-order and speculative processor designs that offer strong provable isolation of software modules running concurrently and sharing resources, even when large parts of the operating system are compromised. Open-source implementations of these processors will allow security properties to be independently verified. Finally, we describe the current limitations of this approach and future opportunities for research.

ESSCIRC ESSDERC Educational Events

Towards Secure High-Performance Computer Architectures

microarchitecture

side channels

computer architecture

secure processors

The Institute of Physics and IOP Publishing, in partnership with the Chinese Physical Society (CPS) and the University of Science and Technology of China (USTC) are proud to have brought together the international quantum science community online for this inaugural conference.


Early career and leading researchers from universities, industry and government worldwide came together to share, learn and collaborate on the latest research and emerging areas of high interest across quantum science and technology. The broad themes covered by Quantum 2020 included:

Quantum communication;
Quantum computing and quantum simulation;
Quantum sensing, metrology and imaging;
Quantum information theory, software and algorithms;
Quantum foundations;
Quantum technology in industry.
The four-day event featured talks from world-renowned scientists, interactive poster sessions and two exciting panel discussions on the themes of Quantum Technology in Industry and Quantum Technology Programmes Around the World.


You will need to [register](https://www.iopconferences.org/iop/frontend/reg/tRegisterEmailNew.csp?pageID=978403&eventID=1552&tempPersonID=536224) to obtain a ticket. . If you have already registered you should have been sent an email from Underline (to the email address that you registered with) with the subject line ‘Welcome to Quantum 2020’. This email includes your ticket for the event. 

If you have a ticket and are experiencing problems in accessing the event, please contact us. 

Quantum 2020

The Institute of Physics and IOP Publishing, in partnership with the Chinese Physical Society (CPS) and the University of Science and Technology of China (USTC) are proud to have brought together the international quantum science community online for this inaugural conference.

Early career and leading researchers from universities, industry and government worldwide came together to share, learn and collaborate on the latest research and emerging areas of high interest across quantum science and technology. 

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This presentation describes the evolving landscape of 77-
81GHz automotive radar transceivers and shows the opportunities and challenges ahead in the quest for higher sensing performance.

77 – 81GHz high performance car radar

Advanced radar solutions for automotive applications

A low-power radar solution for vital signs detection and indoor people sensing is presented. A basic radar theory and design challenges are discussed. How to choose frequency band is explained. System analysis including link budget, dynamic range and LO phase noise, is offered. 
A low power UWB FMCW radar IC is introduced with detailed measurement results as an example.

Low-power 8GHz radar for vital sign monitoring

Millimetre-wave frequency synthesis for RADAR ICs can rely on frequency multiplication. Here the local-oscillator signal – whether a frequency chirp for FMCW or a fixed carrier for PMCW – is first synthesized by a lower-frequency PLL. In case of FMCW, a two-point PLL-based frequency modulator can deliver a large-bandwidth fast chirp, which boosts range resolution and maximal detectable speed. The lower-frequency PLL signal is then distributed and multiplied in frequency at each antenna path. Such a multiplication can be based on harmonic boosting or subharmonic injection locking. All these techniques, which modulate or multiply frequency, are introduced and demonstrated through some implementations in advanced CMOS.

Frequency synthesis for mm-wave radars

This presentation discusses system level considerations about FMCW radar systems. Next, we show two examples of 60GHz CMOS radar and 122GHz BiCMOS radar. Finally, we look into the future and discuss the future development of radar systems.

System and circuit challenges towards high performance radar sensors

As part of the Circuit and systems for RF/mm-wave sensing educational session, in this presentation we focus on the electromagnetic aspects of near-field sensing. We give a high-level overview of the aspects that come into play, approaches that can be used, and challenges, illustrated with examples.

Close proximity methods for RF sensing: an electromagnetics perspective

In this tutorial, entropy generation for ubiquitous hardware security is introduced from first principles to state-of-the-art techniques. Weak and strong physically unclonable functions are presented along with true random number generators.
General trends are analyzed and quantified to identify the most promising solutions for next-generation secure systems. The data presented are based on the HWsecdb public database created and maintained by the research group of the speaker, and are extensively used to make sense of prior art and emerging trends.

Entropy Generation for Ubiquitous Hardware Security

In this talk we survey the concepts of side-channel leakage evaluation and simulation. We present recent simulators and tools for those challenging issues .

Automated power-analysis leakage evaluation and elimination: from Elmo to Rosita

Symmetric cryptography is one of the most used building block today in the field of security. Very often is implemented in hardware, from microcontroller to high end x86 CPU, like the case of AES. From the end of '90 side channel attacks have been presented as a threat to cryptographic implementation, in this presentation we give an introduction to symmetric key cryptography, to side channel attacks, and the new wave of permutation based cryptography and the advanced possibilities of using permutation based crypto for implementing side channel resistant cryptographic hardware.

Cryptographic hardware, Symmetric Cryptography and Side Channel Attacks

This tutorial is to present how chips can be protected against fault injection attacks by using internal sensors.
It gives an overview of sensors to detect different types of fault injection techniques like electromagnetic and laser shots. It presents a generic digital sensor and gives some perspectives for future research topics.

Towards Secure High-Performance Computer Architectures

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Towards Secure High-Performance Computer Architectures

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Next from ESSCIRC ESSDERC Educational Events

77 – 81GHz high performance car radar

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Upper-bounding source side-channel attack on the BB84 decoy-state protocol

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