France

In this tutorial, entropy generation for ubiquitous hardware security is introduced from first principles to state-of-the-art techniques. Weak and strong physically unclonable functions are presented along with true random number generators.
General trends are analyzed and quantified to identify the most promising solutions for next-generation secure systems. The data presented are based on the HWsecdb public database created and maintained by the research group of the speaker, and are extensively used to make sense of prior art and emerging trends.

ESSCIRC ESSDERC Educational Events

Entropy Generation for Ubiquitous Hardware Security

true random number generators

physically unclonable functions

hardware security

low power

internet of things

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





tutorial

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

This presentatio in an introduction to Silicon Photonics for Datacommunication.
Objective is be to review the basics of Silicon Photonics : optical interconnects in datacenter, datarate evolution, the interest of silicon photonics, basic process and main devices physics.


An introduction to Silicon Photonics for Datacommunication

For a long time, there was high expectation of being able to integrate monolithically photonic devices on a single chip, following the path traced by the microelectronics industry.
Unfortunately, process complexity to manufacture photonic chips prevent large-scale production of PICs and the industry remained focused on the single components.
Nowadays the technology allows high level of integration to target a wide variety of applications through the standardization of photonic integration processes for InP and the introduction of process design kits.


Indium Phosphide Technology Platform for Photonics

A semiconductor laser can be modeled as a current controlled oscillator since it can be tuned using its gain section current. Therefore, a semiconductor laser can be phase and frequency locked to a reference laser using an electro-optical phase locked loop (EOPLL). In this talk, some of the EOPLL design challenges such as the effect of the loop delay and laser FM response will be discussed and applications of EOPLLs in optical synthesis and coherent communication will be presented.

Relative Phase Control of Lasers; From Optical Synthesis to Coherent Communication

In this talk, the design of jointly optimized broadband electronics and photonics underlying next-generation (>100GBaud) coherent transceivers is addressed. It is shown how to use SiGe BiCMOS to achieve complex functionality such as interleaving and equalization at analog bandwidths as high as 90GHz. Examples are provided how functionality such as equalization traditionally implemented in the electronics domain can be implemented in a photonic integrated circuit. Finally, options such as micro-transfer printing to densely integrate front-end electronics with optical modulators and detectors are presented.

Co-design and integration of broadband electronic and photonic IC’s for next-generation optical transceiver applications

This presentation describes the evolving landscape of 77-
81GHz automotive radar transceivers and shows the opportunities and challenges ahead in the quest for higher sensing performance.

77 – 81GHz high performance car radar

Advanced radar solutions for automotive applications

A low-power radar solution for vital signs detection and indoor people sensing is presented. A basic radar theory and design challenges are discussed. How to choose frequency band is explained. System analysis including link budget, dynamic range and LO phase noise, is offered. 
A low power UWB FMCW radar IC is introduced with detailed measurement results as an example.

Low-power 8GHz radar for vital sign monitoring

Millimetre-wave frequency synthesis for RADAR ICs can rely on frequency multiplication. Here the local-oscillator signal – whether a frequency chirp for FMCW or a fixed carrier for PMCW – is first synthesized by a lower-frequency PLL. In case of FMCW, a two-point PLL-based frequency modulator can deliver a large-bandwidth fast chirp, which boosts range resolution and maximal detectable speed. The lower-frequency PLL signal is then distributed and multiplied in frequency at each antenna path. Such a multiplication can be based on harmonic boosting or subharmonic injection locking. All these techniques, which modulate or multiply frequency, are introduced and demonstrated through some implementations in advanced CMOS.

Frequency synthesis for mm-wave radars

This presentation discusses system level considerations about FMCW radar systems. Next, we show two examples of 60GHz CMOS radar and 122GHz BiCMOS radar. Finally, we look into the future and discuss the future development of radar systems.

System and circuit challenges towards high performance radar sensors

As part of the Circuit and systems for RF/mm-wave sensing educational session, in this presentation we focus on the electromagnetic aspects of near-field sensing. We give a high-level overview of the aspects that come into play, approaches that can be used, and challenges, illustrated with examples.

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Next from ESSCIRC ESSDERC Educational Events

An introduction to Silicon Photonics for Datacommunication

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