France

While digital synthesis has progressed enormously over the past decades, the synthesis of the analog and mixed-signal circuits has been lagging behind. Despite enormous progress in optimization methods for both analog circuit sizing and analog layout generation, adoption in daily industrial practice has been quite limited. Yet, the growing complexity of integrated systems to be designed today and the growing range of layout constraints introduced by advanced CMOS technologies at 16nm and below increase the need for efficient automated solutions. Also the verification of the designs becomes extremely challenging. Fortunately, novel algorithmic developments, including techniques from machine learning and artificial intelligence, provide the boost towards analog synthesis with increased functionality. Starting from an historical perspective, this presentation will sketch novel developments that aim to boost analog synthesis to the level desired in industrial practice.

ESSCIRC ESSDERC Educational Events

Analog IC synthesis: the return of the Jedi

analog generators

analog layout synthesis

analog ic synthesis

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

After more than 35 years from its first conception and in the year of the recognition with the IEEE milestone, the Smart Power BCD technology is still evolving continuously and rapidly to serve at best the application requirements of new and changing markets.
As stated in the IEEE milestone for “Multiple Silicon Technologies on a Chip, 1985”, STMicrolectronics pioneered the super-integrated silicon-gate process combining Bipolar, CMOS and DMOS (BCD) transistors in single chips for power-demanding applications.
The markets currently requiring faster and higher technology evolutions are the Personal Electronics, bringing needs of wireless charging and power management, the Industrial, asking for more efficient power conversion, and the Automotive, where new challenges come from the battery management and inverter functions in Electric Vehicles and from Autonomous Driving. To meet those market requirements, the Smart Power BCD roadmap is following three key directions: digital processing capability increase (announced 40nm node with embedded non-volatile memory solutions), evolution to higher power and voltage (up to 10kV on-die galvanic isolation) and customization by application. 
We will walk along these three evolution paths, presenting their technology features and related product examples.

The Smart Power BCD evolution in the year of the IEEE milestone

AP&S wet process development on SiC wafers started in 2015 and was initiated by an inquiry from one of the worldwide leading semiconductor manufacturers in Europe. This one was faced with the task of introducing a new production line for microchips based on SiC for a new progressive automotive application. The goal to achieve efficient, high-yield and cost-effective production for SiC products thus has come in focus. One important step in this overall production process has been the reliable and cost-efficient wet processing. The joint development between the semiconductor manufacturer and AP&S, in particular the Demo Center, thus began. This journey took us from metal lift-off process to metal etching processing with endpoint detection on singlewafer application to high-volume batch processing. In this presentation both the changes in the semiconductor manufacturing processes and the solutions derived from them will be presented. Clear breakdowns of the various process data, parameters and conditions will be shown including a detailed overview of the development on SiC from 2015 to 2021.

Wet SiC Metal-Etch - From singlewafer to batch application

Silicon on Insulator is used extensively for its robustness in automotive applications.
X-FAB's BCD on SOI 180nm platform aims at high performance for HV applications and focuses on flexibility and ease of use.
It enables the integration of high voltage BCD devices for driving actuators and motors with high precision analog functions for sensor interface and signal processing. SOI in this context is relevant for its robustness such as latchup immunity and reduced high temperature leakage and also for its isolation properties.
In order to serve our foundry customers, the X-FAB 180nm BCD on SOI platform is highly modular and is fully supported by models, PDKs and design IPs.
When faced with particular operating range constraints, designers can select technology modules to optimize circuit performance for high power/high voltage interfaces.
Besides the traditional ON resistance for a given breakdown voltage, our recent development improved on the usability of the medium and high voltage options with devices ranging from 12V to over 300V. For each geometry the most suitable performance trade-off can be designed with fully characterized and modeled transistors for each voltage classe.
Our technologies are automotive qualified to grade 0 and characterized up to 175oC. We are extending the model validation up to 200oC allowing the design of sensor interfaces and drivers that will operate in a high temperature environment while allowing for dissipation and package thermal resistance.
To support the increase in digital content, non volatile memory IPs are provided either as embedded in the CMOS flow or with a dedicated SONOS module allowing denser implementation. For the SOI platform the memory IP designs are adapted for operation at hot temperature with a specific automotive friendly architecture. 


New results of Bipolar Cmos Dmos on Silicon On Insulator

High performance, low cost solid-state LiDAR systems require novel system architectures regarding sensor and readout circuits in combination with tailored illumination solutions. This talk will focus on performance trade-offs, suitable transmitting units, efficient operating modes and the integration in scalable systems. Elmos Solid State LiDAR concept heads forward to make environment detection smarter to meet upcoming requirements for new ADAS and autonomous driving.
We are presenting a scalable multi-channel laser-driver generating short high intensity pulses for direct time-of-flight measurements. Using a die stacking approach to minimize module size and parasitic inductance, peak currents of up to 50A are applied to the laser-diodes within a 1ns pulse. In addition, the laser driver has integrated functional safety diagnostics including monitoring of the average output power for eye-safe operation.
Implemented in the Elmos automotive-grade 350nm CMOS process, the laser driver is featured in our compact 905nm solid-state LiDAR system for demonstration purposes, which also includes an Elmos-designed SPAD imager.

Sub-nanosecond high-power pulsed multi-channel laser driver for time-of-flight applications

In the last 15 years, Fondazione Bruno Kessler (FBK) has developed a custom technology for single-photon avalanche diodes (SPADs) and silicon photomultipliers (SiPMs) optimized for several applications, from high-energy physics experiments to medical imaging or light detection and ranging (LiDAR). In the IPCEI framework, FBK is upgrading its microfabrication facility for the realization of 3D integrated radiation sensors. In the specific case of SiPMs, 3D integration technologies will allow to improve its capabilities by using back side illuminated (BSI) devices and Through Silicon Vias (TSV) interconnections. The BSI approach for SiPMs can be exploited to improve the current photon detection efficiency (PDE), even in the wavelength ranges far away from the visible spectrum, where typically it drops down to about 10% for the near infrared (NIR) and about 15% for vacuum ultraviolet (VUV). A first batch of BSI SiPMs for NIR detection was recently fabricated at FBK as a proof of concept. After wafer bonding and thinning, the characterization results showed an increase of the PDE of about 50% at 900 nm for BSI sensors with metal reflectors compared with the standard front side illuminated (FSI) technology. Research on the realization of the fabrication process modules optimized for near ultraviolet (NUV) and VUV BSI SiPMs is currently ongoing and will also be presented and discussed.

Back side illuminated SiPM from NIR to NUV light detection

Requirements towards chip separation are getting more and more complex in recent years. The increasing trend for lower chip thickness and different backside metal stacks leads to a big variety in processes and material combinations interacting with each other. Unwanted interactions can even block the overall manufacturing flow of chips in module or package assembly.
With the newly presented method on chip level it is now possible to measure in detail the release process of chip from the dicing tape during pick-up and to determine the influence of unit processes like dicing or UV irradiation and their interaction effects on the die bond process during assembly. In this presentation we will focus on the effect of different stress release processes and show the effect of different UV chambers on the UV curing of dicing tapes.

Characterization of Preassembly influence on Die Attach process

LYNRED product offer covers a large span of applications, in cooled and uncooled infrared domains. The presentation will focus on two detectors addressing two different infrared technologies:
 First - « Key elements for hybridization technology development of 2000x2000 pixels Infrared Focal Plane Arrays”..
 Then a LWIR camera module will be presented: an uncooled bolometers detector stacked with a custom IR image processor (ISP). The ISP is a dedicated ASIC built to apply a pipeline of image processing algorithms to the raw sensor data which corrects for pixel defects and non-uniformities in the sensor, without requiring to an external mechanical shutter. With this approach, LYNRED demonstrates an easy-to-use, plug-and-play solution


Lynred Advanced Developments in the Field of Infrared Imaging Technologies

For more than 50 years, Moore's Law has been driven by resolution improvements of lithography scanners which generate an image of the lithography mask on the semiconductor wafer. This image contains the patterning information needed to build up an integrated circuit.
The latest scanner generation uses 13.5 nm light at 0.33NA. Since the last 2 years they are now essential to produce leading edge semiconductor devices. To further increase the resolution ZEISS is working on next generation EUV optics. This optics consists of a highly flexible illumination system and projection optics with NA 0.55 enabling single-exposure sub 8nm half-pitch resolution to allow scaling beyond the next decade.
In this presentation we will explain the system design of the high-NA optical column and we will report on the manufacturing status of mirrors and frames. Furthermore, the buildup of the infrastructure including mirror polishing, coating, surface figure metrology, mirror handling, and integration tooling will be shown.

High NA EUV optics: preparing lithography for the next big step

Biological networks of neurons and synapses have the capacity to process multiple operations through short electrical pulses, also referred to as “spikes”, with very low energy consumption. Spiking Neural Networks (SNN) are a new form of Artificial Intelligence (AI) that aim to replicate these cognitive features in order to improve next generation computer’s performance. We present the design and simulation of an individual spiking laser to be used as a photonic neuron for a SNN scale-up. The neuron is a semiconductor laser optimized for pulsed operation through modification of the CEA Leti III-V on Si integrated continuous wave laser's heterostructure. A first demonstration of its neural features connected with synaptic functions is also reported.

Pulsed lasers neurons integrated on silicon for dense spiking neural network

LEDs for the UV-C spectral range gained increased attention in the recent years due to potential applications regarding the CoVID-19 pandemic. While its wide commercial uptake of UV-C LEDs is still inhibited by their relatively small efficiencies and lifetimes compared to conventional UV-light sources and compared to LEDs emitting in the visible spectral range, many improvements in the semiconductor device (LED chip and package) performance yield an accelerated entry into various markets.
The presentation will highlight the improvements enabling the achieved significant improvements in UV-C LEDs, such as crystalline quality of the chips, operation voltage, output power, lifetime and stability of their fabrication processes. 
The major application for UV-C LEDs is the large field of UV disinfection due to their UV-C radiation. Beyond this there are various other application fields. In the past years UV LEDs successfully entered other applications like streetlighting, horticulture lighting and general lighting. It always started as the underdog and a direct comparison with conventional sources was difficult and barely in the benefit of the new source. But again, the completely different properties of LED light sources are showing significant benefits in new system designs which have not been possible before.
Benefits of distinct UV-C LED sources and arrangements in different systems will be presented by explaining the features which enable the light source to be competitive and even perfectly suited for various disinfection applications.


Analog IC synthesis: the return of the Jedi

Downloads

Next from ESSCIRC ESSDERC Educational Events

The Smart Power BCD evolution in the year of the IEEE milestone

Similar lecture

A 1.67-GSps Ti 10-Bit Ping-Pong SAR ADC with 51-dB SNDR in 16-nm FinFET

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Analog IC synthesis: the return of the Jedi

.css-70qvj9{display:-webkit-box;display:-webkit-flex;display:-ms-flexbox;display:flex;-webkit-align-items:center;-webkit-box-align:center;-ms-flex-align:center;align-items:center;}Downloads

Next from ESSCIRC ESSDERC Educational Events

The Smart Power BCD evolution in the year of the IEEE milestone

Similar lecture

A 1.67-GSps Ti 10-Bit Ping-Pong SAR ADC with 51-dB SNDR in 16-nm FinFET

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads