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ESSCIRC ESSDERC Educational Events

IoT: Promises, Challenges and Solutions

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The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

Please register for educational events at the following link: https://www.registerme.eu/event/esscirc-essderc-2021/

Please register for the ESSCIRC/ESSDERC Educational Events to join the event.

The Educational Events of ESSCIRC ESSDERC 2021. 

The explosive growth in the size of Artificial Intelligence (AI) models and the concomitant increase in compute intensity over the past few years is unsustainable without significant innovation across the stack. A non-von Neumann computational approach using in-memory compute is a paradigm shift that can deliver significant improvements in performance and energy efficiency for data-centric AI applications. Among the many memory options being evaluated, phase change memory (PCM) devices are attractive given their non-volatility, analog tunability & maturity of the technology. However, these devices also suffer from many non-idealities. This talk details innovations across materials, algorithms and architecture to address challenges posed by PCM device non-idealities to accelerate AI inference and training jobs.

Device, Architecture, and Algorithms Co-optimization for Scalable Analog Compute Technology

Computing-in-memory (CIM) is being widely explored to minimize powerconsumption in data movement and multiply-and-accumulate (MAC) for AI edge devices. In my talk, I will introduce several design techniques for CIM including both analog and digital approaches.

Basic introduction of SRAM based CIM including analog and digital approach

Artificial intelligence and deep neural networks (DNNs) have been successful across many practical applications, but state-of-the-art algorithms are compute-/memory-intensive. In-memory computing (IMC) has emerged as a promising technique to resolve the computation and memory access bottleneck. While many single-macro-level IMC prototypes have been demonstrated, integration and programmability challenges remain for system-level IMC accelerators. To that end, we present a programmable IMC accelerator (PIMCA) integrating 108 capacitive-coupling-based IMC SRAM macros of a total size of 3.4 Mb, demonstrating one of the largest IMC hardware to date. We will discuss architecture design and techniques employed for the PIMCA chip design, including a custom ISA featuring IMC and SIMD functional units with hardware loop to support a range of DNN layer types. The 28nm prototype chip achieves high system-level peak/average energy-efficiency of 437/289 TOPS/W.

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference

When it comes to modelling materials of technological interest for microelectronics and their properties, the challenge is great, especially when considering current low-temperature processes, 3D architectures for the integration of ultra-thin, nanostructured materials with controlled performance. The continuum methods on which TCAD simulation in industrial environments typically relies are inherently unable to capture the resulting effects at these scales such as defect formation and growth mechanisms. 
In this talk, we will see how it has become necessary to implement a series of atomistic tools at different time and size scales to capture all the effects necessary for reliable process prediction. A review of atomistic methods will be proposed from the most conventional methods such as molecular dynamics and DFT to state-of-the-art methods such as going “beyond DFT” and Machine Learning potential. Examples on manufacturing process and defects characterization will be given.
Finally, one the main purpose of these studies is to help microelectronics engineers. Example of implementation of atomistic data into industrial TCAD tools will be given and discussed.

What multi-level strategy for modelling processes and defects in semiconductors at the atomic scale? Current approaches, necessary developments and new needs.

Advances in process and fabrication enable the relentless downscaling into the nanometer regime and open the way to a new era of device structures and materials. Approaching the atomic scale, individual imperfections such as point defects, which are inevitably present in bulk and interface systems, and their distributed properties start to become a decisive factor for device reliability and start to dominate the device performance. Keeping pace with the technological progress on the theoretical simulation side, hence, requires reliable approaches based on fundamental physics such as ab initio calculations. Largely driven by the beat of Moore’s law itself and the increase of computational resources, atomistic first-principles calculations are routinely used nowadays to predict structural and electronic properties. Nevertheless, understanding the underlying model together with a careful analysis of the results is essential to draw meaningful conclusions. Particularly in the field of device reliability, these advancements have enabled an improved understanding of intrinsic and extrinsic point defects in various materials such as Si/SiO2/HfO2 or SiC/SiO2 stacks. Due to the predictive power and accuracy of density-functional-based calculations characteristic defect properties such as thermodynamic and optical transition levels as well as their interaction with the surrounding can be directly connected to experimental observations. Hence, it is possible to assess how vacancy, interstitial, antisite, substitutional, and other defect types impact and perturb the device performance. Moreover, these results provide vital input for the development of modern predictive TCAD models.

Modeling of Bulk and Interface Defects for Reliability Prediction on the Atomistic Scale.

The current electronic device scaling is reduced to 5 nm and smaller technology nodes based on EUV lithography, it is expected to reach sub-nm technology node within a decade. Along with the EUV scaling, the space of medium/upper level BEOL provides both challenges and opportunities to device research community. Rational design of device materials using atomic scaling modeling methods can contribute the accelerated development of the new technology materials based on fundamental understanding on their atomic and electronic scale properties. Using the density functional theory (DFT), atomistic kinetic Monte Carlo (KMC) and time-dependent DFT (TDDFT) simulations methods, we have been investigating the BEOL process compatible oxide semiconductors for monolithic 3 dimensional (M3D) integration of functional devices in the intermediate interconnect layers. In this tutorial, we will discuss about the multiscale modeling approaches applied to device materials modeling for n- and p-type oxide semiconductor design for BEOL applications. We will examine atomic and electronic structures of both n-type and p-type oxide semiconductors in crystalline and amorphous phases. Using the rational design approach to oxide semiconductors based on DFT calculations, we are exploring the complex oxide material parameter space and charting possible pathways to develop both p-type and n-type oxide semiconductor candidates for BEOL CMOS applications. We will discuss the design rationales of currently identified oxide semiconductor candidates (Ta2SnO6, TiSnO3 for p-type In-W-O system for n-type) and validation experiments to accelerate the focused development of BEOL oxide semiconductors with superior performance. These oxide semiconductors will provide case study examples of the materials deign method applied to electronic device materials in this tutorial. 
This work was supported by ASCENT, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Rational Design of BEOL Oxide Semiconductors for Emerging Device Applications.

It is well known that, over a wide range of wavelengths, a graphene sheet absorbs 2.3% of the light passing through it. This value is directly related to the fine structure constant, which can be interpreted by the very particular band structure of this material. Remarkably, it has been shown experimentally that thin InAs films exhibit an aborption spectrum characterized by steps that can also be related to the fine structure constant. We present numerical simulations (TB, KP) showing that this phenomenon is very robust and is obtained for a very large number of semiconductor materials. We complement this work with analytical calculations to understand the physical origin of this behavior. The comparison with graphene is discussed.

Optical absorption quantization in nanolayers of semiconductors

Halide perovskite semiconductors, either fully inorganic or hybrid organic-inorganic, have attracted a lot of interest since 2012 owing to their excellent performances for photovoltaic applications. These low-cost semiconductors have attractive intrinsic physical properties for optoelectronics, including direct band gaps, small effective masses, large carrier mobilities, sizeable optical absorption and quantum yield for luminescence. Available tools, including commercial codes, for semiconductor device simulations provide reasonable descriptions of the perovskite device characteristics under operation. However such simulations are still hardly predictive. The aim of the presentation will be to give an overview of the current challenges for such simulations by comparison to classical semiconductors, including 1) the diversity of compositions, nanostructure dimensionalities, crystallographic structures or processing of the perovskite materials, 2) the unusual physical properties of this new class of soft and ionic semiconductors, 3) the primary importance and complexity of the interfaces in perovskite-based thin film heterostructures

Perovskite semiconductors: current challenges for predictive atomistic and device simulation.

Computer simulations are well established to support experimental R&D in OLED and OPV technology: On the molecular scale, quantum chemistry tools such as DFT are used to compute molecular properties such as HOMO or levels or excitation energies, while continuum models, e.g. drift diffusion, are efficient tools for virtual design on the device level. 
However, the application of quantum chemistry methods is limited to a few molecules at best, prohibiting the direct computation of material properties in thin films and their impact on device performance. Continuum models on the other hand rely on parametric models which often need to be calibrated with experiments due to the lack of predictive microscopic models. 
We bridge this gap of scales using a multiscale workflow that connects fundamental chemistry and device design: Using a physical vapor deposition protocol with customized force-fields and a quantum embedding scheme we generate digital twins of OLED layers and devices. For these digital twins we compute electrical properties such as electron affinity, ionization potential and permittivity. Using a kinetic Monte-Carlo protocol we conduct virtual experiments on the digital twins to simulate charge carrier and exciton dynamics in OLED devices to e.g. compute charge carrier mobility or device efficiency. These microscopic simulations generate a fundamental understanding on how molecular properties trigger and balance microscopic processes, thereby enabling materials and device designers to systematically eliminate bottlenecks in OLED performance. Further, the multiscale workflow can be used to parametrize continuum models from first principles, facilitating full virtual design.

Connecting quantum chemistry and device level simulations via multiscale simulation workflows

This tutorial will focus on how to determine the dielectric, electronic transport, and magnetic properties of two-dimensional (2D) materials from first principles using density functional theory (DFT). We will exhibit a simple yet robust methodology to extract the dielectric constant of a monolayer/few-layer structures from a DFT calculation. We will illustrate the dielectric constant methodology by determining the low- and high-frequency dielectric constant of hexagonal boron-nitride, transition metal dichalcogenides (TMDs), and novel unexplored dielectrics. Next, we will show how our open-source Plane-wave Electron TRAnsport (PETRA) quantum transport code can be used to simulate transport in nanowires and nanoribbons. Finally, we will show how from DFT calculations for various magnetic configurations, the exchange interaction can be described as a function of concentration. Once the exchange interaction description is determined, Monte Carlo simulations can be performed to determine the magnetic order and the Curie/Néel temperature, the magnetic properties of layered materials can be determined. We will illustrate the approach using monolayer MoSe2 and show that five different magnetic orderings in 2D materials are revealed.

IoT: Promises, Challenges and Solutions

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IoT: Promises, Challenges and Solutions

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Next from ESSCIRC ESSDERC Educational Events

Device, Architecture, and Algorithms Co-optimization for Scalable Analog Compute Technology

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A Wide Tuning Range Delay Element for Event-Driven Processing of Low-Frequency Signals in 28-nm FD-SOI CMOS

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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