Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9205866

**Abstract:**

The use of new materials with advanced properties has become mandatory to meet the needs for higher electronics performance at reduced power. Topological insulators (TIs) possess highly conductive topologically protected edge states which are insensitive to scattering and thus suitable for energy-efficient highspeed devices. Here,we evaluate the subband structure in a narrow nanoribbon of 1T molybdenumdisulphide using an effective k·p Hamiltonian. Highly conductive topologically protected edge modes whose energies lie within the bulk band gap are investigated on equal footing with traditional electron and hole subbands. Due to the interaction between the edge modes at opposite sides, a small gap in their linear spectrum opens up in a narrow nanoribbon. This gap is shown to sharply increase with the perpendicular out-of-plane electric field, in contrast to the behavior in a wide nanoribbon with negligible edge modes’ interaction. This increase leads to a rapid decrease in the ballistic nanoribbon conductance and current with the electric field, which can be used for designing molybdenum disulphide nanoribbon-based current switches.

ESSCIRC ESSDERC 2021

Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T\&#39; Phase

ballistic conductance.

k.p hamiltonian

subbands

nanoribbons

topologically protected edge states

topological insulators

[![](https://assets.underline.io/uploads/markdown_image/1/image/985c8a40b04e56675221c8549975de3c.png)](https://drive.google.com/file/d/1B70nPIeeeqdG4UU70NlYXuKVOHLRuJEo/view?usp=sharing)

### ** History of DRC**
The Device Research Conference (DRC) began in the pre-transistor era with the 1942 establishment of the Conference on Electron Device Research (CEDR). Following William Shockley’s 1948 CEDR presentation of the transistor device, the Solid-State Device Research Conference (SSDRC) was established, with invitation-only attendance.

In the ensuing decades, many exciting firsts were presented at SSDRC, including the use of impurity diffusion in silicon and germanium, the first practical MOSFET, and the first lattice-matched heterojunction.

In 1969, under the leadership or Herbert Kroemer and Cal Quate, the CEDR and SSDRC merged into DRC. In 1970, attendance was opened to all, and the first DRAM (dynamic random-access memory), room temperature lasers, and first CCD (charge-coupled device) were reported—all in the same 1970 DRC meeting!

1976 saw the first official coordination of tandem meetings between DRC and the Electronic Materials Conference (EMC) to bring together the electronic materials and device communities—a custom which persists to this day. In 1991, DRC began publishing its digest with IEEE; they can all be found [here on IEEE Xplore](https://ieeexplore.ieee.org/xpl/conhome/1000199/all-proceedings). Throughout this period, DRC featured reports of many novel and record-setting devices, including the HEMT (High Electron Mobility Transistor), VCSEL (Vertical Cavity Surface Emitting Laser), HBT (Heterojunction Bipolar Transistor), and nanoscale MOSFETs.

In recent years, DRC has continued to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an [article in the Journal of the Electron Device Society](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486). DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Today, as we look forward to the next 75+ years of device innovation, DRC continues to lead the way in showcasing top-caliber research, facilitating vibrant discussion and debate and acting as a platform to nurture the next generation of device engineers. We welcome you to join us at the next DRC!

To learn more about DRC's history, please see [Aaron Franklin, Debdeep Jena and Deji Akinwande, "75 Years of the Device Research Conference—A History Worth Repeating," in IEEE Journal of the Electron Devices Society, vol. 6, pp. 116-120, 2018. doi: 10.1109/JEDS.2017.2780778](https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8168249&isnumber=8232486).

### **Topics**
* Biological Devices
* Devices for Extreme Conditions
* Heterogeneously Integrated Devices
* Memory Devices
* Modeling and Simulation of Devices
* Nanoscale and Vacuum Devices
* Optoelectronic and Optical Devices
* Other Emerging Devices
* Power Devices
* Quantum Devices
* RF and Terahertz Devices
* Spintronic and Magnetic Devices
* Thin-film Devices
* Wide-bandgap Devices
 
### **Invited Speakers**
* Patrick Fay, University of Notre Dame
* Susanne Hoffmann-Eifert, Peter Grünberg Institute
* Sanghyeon Kim, Korea Advanced Institute of Science and Technology
* Sriram Krishnamoorthy, University of California, Santa Barbara
* Mario Lanza, King Abdullah University of Science and Technology
* Xiuling Li, The University of Texas at Austin
* Marko Radosavljevic, Intel Corporation
* Siddharth Rajan, The Ohio State University
* Giordano Scappucci, Delft University of Technology
* Fisher Yu, University of Arkansas
* Wenjuan Zhu, University of Illinois at Urbana-Champaign




Registration is required to attend this event. If you have not already done so, please use the link below to register for a ticket to the conference:

https://www.mrs.org/drc-2022/registration

Registration Is Required

DRC 2022

DRC continues to be the world’s premier forum to present innovative semiconductor device research with work on organic thin film transistors, graphene and carbon nanotube transistors, and 2D materials all featuring prominently in the 1990s through to the present day. In 2017, we celebrated DRC’s 75th anniversary with special sessions and an article in the Journal of the Electron Device Society. 
DRC technical topics continue to evolve with emerging device trends such as memory devices, quantum devices, optoelectronics/photonics, and wide bandgap power devices to reflect the exciting work being done by a diverse community of device engineers around the globe.

Conductance in a Nanoribbon of Topologically Insulating MoS2 in the 1T\' Phase

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9161.pdf

**Abstract:**

This paper presents a transmitter concept which generates a wide coherent modulation bandwidth. The proposed FDDAC based Tx concept exploits the relation between the discrete and continuous-time Fourier Transform leading to intrinsic Nyquist filtering. Thus, the sampling rates in the analogue-mixed-signal and the DSP domains are reduced by up to two orders of magnitude compared to conventional Txs. The experimentally verified integrated Tx-IC for 802.11ad/y applications generates a single-carrier 16QAM signal with a modulation BW of up to 2GHz. The measured EVM values are 7.2% and 11.8% for a 1 and 2GHz QPSK signal, respectively, whereas they are 9.6% and 13.9% for a 1 and 2GHz-wide 16QAM signal.

FDDAC-Based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9113.pdf

**Abstract:**

Noise-shaping is essential for Direct Digital to RF (DDRF) transmission but filtering of Out of Band (OOB) quantization noise is difficult at 6 GHz for Wi-Fi 6E. We present a filter-free DDRF architecture that introduces targeted noise-shaping (TaNS) to meet the spectral mask. TaNS attenuates quantization noise at offsets between one and ten times the bandwidth by moving it far out-of-band. The prototype is fabricated in 28nm CMOS with an active area of 0.022 mm2 and shows the feasibility of 64-QAM modulation up to 281 Mbps.

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9157.pdf

**Abstract:**

As wireline transceivers continue to push for higher speeds, their power consumption becomes increasingly more critical. This paper describes methods that can reduce the power drawn by drivers and multiplexers on the transmit side and equalizers and clock and data recovery circuits on the receive side. These concepts have been incorporated in designs ranging from 40 Gb/s to 80 Gb/s in 45-nm and 28-nm process nodes.

Low-Power Techniques for Wireline Systems

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9168.pdf

**Abstract:**

This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9134.pdf

**Abstract:**

This article presents a 64-Gb/s PAM-4 TX with a proposed 4-tap hybrid feed-forward equalization (FFE). The pre-emphasis (PE) based FFE is employed to enlarge the output swing by directly stacking the distorted pulses on the main pulse. And it consumes less power than the de-emphasis (DE) based counterpart as it only boosts the desired distorted symbols. The fractionally-spaced (FS) based FFE provides compensation of signal beyond Nyquist and the post2 tap compensates for the lower-frequency signal, the combination of them realizes an accurate equalization and wide compensation range.

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178737

**Abstract:**

A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this work. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring-oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of signal-band and also has intrinsic interferer rejection capability. A prototype ADC fabricated in 65nm CMOS is operated at an IF of 52MHz. The ADC has an SNDR of 63.1dB and 59.5dB at 1.04MHz and 4.3MHz bandwidth, respectively. The ADC consumes only 0.36mW power from a 0.9V supply and has an energy efficiency of 21fJ/step improving upon the current state-of-the-art by 3.5x.

21fJ/Step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9137304

**Abstract:**

This paper introduces a novel SAR-based algorithm that speeds up the conversion by using two digital-to-analog converters that operate in a ping-pong fashion. It has been implemented in a 4x time-interleaved analog-to-digital converter in a 16-nm FinFET technology. Each channel uses the proposed ping-pong SAR (PP-SAR) algorithm in a coarse phase followed by a comparator-based asynchronous binary search (CABS) fine phase to realize 418 MHz/channel 10-bit conversion with 51-dB SNDR at Nyquist. The total power consumption is 7.9 mW corresponding to a Walden FoM of 16 fJ/conversion-step at Nyquist.

A 1.67-GSps Ti 10-Bit Ping-Pong SAR ADC with 51-dB SNDR in 16-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9183905

**Abstract:**

This letter presents a compact buffer-less 12-bit output SAR-based bridge-to-digital converter. Eliminating the sample-and-hold circuit substantially simplifies the sensor front-end by providing a high impedance input stage. The binary weighted digital-to-analog converter (DAC) is replaced with a switched-capacitor DAC which is driven by an error-feedback modulator. This alleviates mismatch issues and provides area and power savings when used with a Wheatstone bridge as a read-out. The converter has a wide input range of 830 mV making it suitable for gas sensor applications. It is realized in 65-nm CMOS, occupies 0.01 mm2 area, and consumes 6.2 μA with a 45 ms conversion time. It achieves 9.1 ENOB for a DC input and a Walden FoM of 0.65 nJ/conv-step.

A 0.01-mm2 0.83-V Input Range SAR-Based Bridge-to-Digital Converter

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171283

**Abstract:**

This work presents a simplex and a full duplex digital communication interface that enhance the energy efficiency of chip-to-chip digital communication in low speed low power systems. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5^10-12. The simplex and full duplex interfaces achieve an energy consumption of 0.38pJ/b and 1.2pJ/b respectively. The simplex interface achieves a power reduction of 2× to 27× compared to conventional LVCMOS for data rates from 10kb/s to 50Mb/s. The full duplex interface achieves a power reduction of 5× to 11× for data rates from 100kb/s to 50Mb/s.

A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9160876

**Abstract:**

The data rate-times-distance product in mm-wave dielectric waveguide (DWG) communication links is usually limited by waveguide dispersion. This letter presents the DWG\'s baseband impulse response in the context of a homodyne receiver and introduces a continuous-time linear equalizer able to minimize such dispersion. The desired transfer function is implemented with inverter-based transconductance cells. The simulation and measurement results at 10-Gbps data rate show eye-opening improvement at two distances (10 and 15 m) and carrier frequencies (140 and 160 GHz). The equalizer occupies 80 × 32 μm2 in GLOBALFOUNDRIES 22-nm FD-SOI.

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FDDAC-Based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate

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Next from ESSCIRC ESSDERC 2021

FDDAC-Based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate

Similar lecture

Late News: A Gate-All-Around Single-Channel In2O3 Nanoribbon FET with Near 20 mA/µm Drain Current

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

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