Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9170592

**Abstract:**

We present a digital cell library optimized for 4.2 K to create controllers that keep quantum processors coherent and entangled. The library, implemented on a standard 40nm-CMOS technology, was employed in the creation of the first 4.2 K RISC-V processor. It has achieved a minimum supply voltage of 590mV, energy-delay product of 37fJ/MHz, and maximum operating frequency of 740MHz, all at 4.2 K in continuous operation. These results have been obtained from stand-alone characterization, successfully executing small C programs/benchmarks at 4.2 K. The overall performance of the library compares well against state- of-the-art libraries designed for room temperature. In particular, we compared the performance of the proposed library against a foundry supplied library for the same process in several combinational benchmark circuits, showing significant improvements in power dissipation and frequency of operation.

ESSCIRC ESSDERC 2021

A Cryo-CMOS Digital Cell Library for Quantum Computing Applications

cmos library

cryogenic electronics

risc-v

cryo-cmos

quantum computing

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9269.pdf

**Abstract:**

We present a 2T0C IGZO based Capacitor-less memory that enhances the sensing margin and retention time for DRAM applications requiring higher data immunity. In the proposed technique for increased data integrity, the Read Bit-Line (RBL) is precharged at Half-VDD, instead of Full-VDD, to utilize the rising edge of read word line (RWL) at the beginning of read. This increases the storage node potential of the bit-cell (due to coupling between RWL and the storage node) which is otherwise degraded at write termination due to coupling of write word line (WWL) and the storage node.

Enhanced Data Integrity of In-Ga-Zn-Oxide Based Capacitor-Less 2T Memory for DRAM Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9029.pdf

**Abstract:**

A fast charge loss during short time retention operation was observed in word-line stacked 3-D NAND flash memory, and the origin of the fast charge loss was comprehensively evaluated. Using a fast-response pulse I-V system, the fast charge loss behaviors from lateral and vertical migration of trapped charges were thoroughly investigated and measured at various program/erase levels and temperatures in solid and checkerboard pattern.

Vertical and Lateral Charge Losses During Short Time Retention in 3-D NAND Flash Memory

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9189.pdf

**Abstract:**

This paper presents a comparison of array-level performance of non-volatile SOT-MRAM and SOTFET-RAM to conventional 6T CMOS SRAM using a specially developed simulation suite that merges physics-based compact models and layout-based parasitic extraction. Unlike prior work, our characterization framework generates a full layout of the memory array including all peripheral logic and routing. The framework uses an industry-standard parasitic extraction tool to generate the full netlist including parasitics which is then simulated using compact models for the appropriate emerging non-volatile device. Using this framework, we show about 1.8X energy savings for total read operations and write operations, and 2X area savings for the SOT-based memories relative to a comparable CMOS SRAM for a 256X128 array size. Our unique full-layout approach also enables important insights that challenge conventional wisdom based on higher-level modeling.

Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9231.pdf

**Abstract:**

Ge MFS capacitors with ultrathin ferroelectric HZO are prepared to fabricate FTJ devices. 5 nm HZO after wake-up show good reliability and excellent polarization switching characteristics featuring high remanent polarization Pr~ 22.2 μF/cm2 and low coercive voltage Vc ~ 1.1V. These performance characteristics create the prospect for low voltage (<2 V) /low power NVM FTJ memories. According to our modeling, 5 nm FTJs suffer from low Jon, but thinner HZO devices combine high Jon (>0.1 A/cm2) and relatively large TER (>70). A sufficiently large Jon has been measured on our 3-nm HZO FTJs, albeit with lower-than-expected TER and Ion/Ioff ratios.

Scaling Ferroelectric HZO Thickness for Low Power Ge MFS-FTJ Memories

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9220.pdf

**Abstract:**

In this paper, artificial synapses based on 4-terminal ferroelectric Schottky barrier field effect transistors (FE-SBFETs) are experimentally demonstrated. The ferroelectric polarization switching dynamics gradually modulate the Schottky barriers, thus programming the device conductance by applying positive and negative pulses to imitate the excitation and inhibition behaviors of biological synapse, respectively. The excitatory post-synaptic current can be tuned by the back-gate bias, enabling the reconfiguration of the weight profile with high speed (20 ns) and low energy (< 1 fJ) consumption. Besides, tunable long term potentiation and depression with high endurance and low cycle-to-cycle variations are achieved. These findings demonstrate FE-SBFET has high potential as an ideal synaptic component for the future intelligent neuromorphic network.

4-Terminal Ferroelectric Schottky Barrier Field Effect Transistors as Artificial Synapses

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9239.pdf

**Abstract:**

We present an innovative mechanism to remove electric charges from SRAM bitcells. The particularity of this countermeasure is to be compatible with SRAMs designed from foundry bitcells. We have designed and characterized an 8kB SRAM in 22nm FD-SOI technology exploiting the proposed security strategy demonstrating an erase operation accomplished in the ns time scale (versus 295µs using conventional power-off) with an additional area <5%. We have also shown the better efficiency of our solution compared to a solution without prior erasure. The use of the latter drops the ratio of zeroized addresses at 92%, while increasing energy consumption by 2.1x.

A Near-Instantaneous and Non-Invasive Erasure Design Technique to Protect Sensitive Data Stored in Secure SRAMs

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9229.pdf

**Abstract:**

A 32 Kb dual-port low-voltage SRAM in 28nm FD-SOI, featuring foundry supplied high-density 6T bitcells, is presented. Dual-port configurability is realized by a unique dual-rail architecture, utilizing boost techniques that guarantee reliable operation in low-voltage. The area cost of the array is 62% lower, compared to widely used 8T two-port or dual port SRAM arrays. The SRAM reliably operates in the low-voltage regime, and an access rate of 1MHz is measured at VMIN of 0.29V. The highest energy efficiency of 1.35 fJ/bit-access is obtained at 80MHz access rate, at a VDD of 0.54V.

A Low-Voltage 6T Dual-Port Configured SRAM with Wordline Boost in 28 nm FD-SOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9098.pdf

**Abstract:**

In this paper, a quadrature error corrector (QEC) for next generation DRAM interface is proposed. The proposed QEC corrects duty-cycle error and 4-phase skew simultaneously for high speed operation in DRAMs. The internally used half rate two-phase clocking reduces power by 35% and area by 40%, respectively. A prototype chip achieves less than 1.84˚ phase error for a 12.8 Gb/s and has a correctable range 100.5˚ within 120 ns lock-time using successive approximation register (SAR). A re-lock scheme to cope with voltage and temperature variation during chip operation is also proposed. It occupies an active area of 0.01 mm2 while consuming 9.8 mW with 1.0-V supply.

A 3.2-12.8Gb/s Duty-Cycle Compensating Quadrature Error Corrector for DRAM Interfaces, with Fast Locking and Low Power Characteristics

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9204657

**Abstract:**

In this work, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film siliconon-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: the Effect of Back Bias on Drain Current and Transconductance

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9201379

**Abstract:**

This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning is found to be temperature independent, allowing extra drain current improvement. This is particularly interesting for short channel devices, whose drain current gain with temperature lowering is expected to be smaller in comparison with long channel MOSFETs. LFN is characterized by means of time-domain current sampling measurements. Moderate and strong inversion regimes are investigated. The carrier number with correlated mobility fluctuations model can well describe the 1/f noise behavior down to 4.2 K. The physical origin behind the drain current noise-to-signal power augmentation with temperature lowering could be mainly attributed to the normalized transconductance improvement.

A Cryo-CMOS Digital Cell Library for Quantum Computing Applications

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