Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9189.pdf

**Abstract:**

This paper presents a comparison of array-level performance of non-volatile SOT-MRAM and SOTFET-RAM to conventional 6T CMOS SRAM using a specially developed simulation suite that merges physics-based compact models and layout-based parasitic extraction. Unlike prior work, our characterization framework generates a full layout of the memory array including all peripheral logic and routing. The framework uses an industry-standard parasitic extraction tool to generate the full netlist including parasitics which is then simulated using compact models for the appropriate emerging non-volatile device. Using this framework, we show about 1.8X energy savings for total read operations and write operations, and 2X area savings for the SOT-based memories relative to a comparable CMOS SRAM for a 256X128 array size. Our unique full-layout approach also enables important insights that challenge conventional wisdom based on higher-level modeling.

ESSCIRC ESSDERC 2021

Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM

post-cmos

sotfet

mram

cmos

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9228.pdf

**Abstract:**

Body-coupled powering (BCP) via the human body channel has demonstrated improved pathloss and body-area coverage over conventional approaches. This work focuses on dynamic optimization of the transmitter (hub-side) output power and frequency, to avoid power overdraw for prolonged transmitter (hub) lifetime. Power evaluation and feedback allow the transmitter to dynamically adapt its power and frequency, based on the node-specific channel and power condition, with only ~90nW overhead. This saves the overall TX power by 7×. Moreover, HV driver with simplified driving circuits is proposed in standard CMOS process, which allows for 20× improved power delivery (at 105cm) while saving 23% of the TX power consumption. The body-coupled power transceiver (TRX) ICs are implemented and measured in 40nm CMOS process.

Body-Coupled Power Transceiver with Node-Specific Body-Area Powering

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9018.pdf

**Abstract:**

This paper presents a fully integrated dual-band transceiver (TRX) with mutually-coupled on-chip antennas for implantable and wearable devices. It operates at 915 MHz and 2.4 GHz in both transmit and receive modes to enable bidirectional communication between medical and consumer electronics using a single chip. The TRX is fabricated in 180 nm CMOS along with a power management unit (PMU) with a size of 2.4x1.9 mm2. The transmitter (TX) consists of a mutually-coupled dual-band oscillator and uses the on-chip antennas as the inductors of the oscillators. The maximum uplink data rates of the TXs are 20 Mb/s and 40 Mb/s for 915 MHz and 2.4 GHz, respectively, with corresponding TX efficiencies of 62 pJ/b and 35 pJ/b. The maximum achievable downlink data rates are 2 Mb/s and 1 Mb/s for 915 MHz and 2.4 GHz, respectively, resulting in 2 pJ/b and 4 pJ/b of energy efficiencies. Importantly, the proposed TRX achieves uplink and downlink communication ranges of 30 cm and 17 cm for the 915 MHz band, and of 38 cm and 2 cm for the 2.4 GHz band, respectively.

Dual-Band Transceiver with Mutually-Coupled On-Chip Antennas for Implantable/Wearable Devices

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9076.pdf

**Abstract:**

This paper presents a widely tunable bandpass filter (BPF) that can autonomously adapt its gain to the power level of signals present within its passband. Similar to outphasing amplifiers, the filter realizes reconfigurable gain by splitting the input signal using two N-path filters into two components of equal and opposite phases (±Φ). The components are then subtracted at the filter output to reconstruct the original signal with a gain value proportional to sin(Φ).

A Self-Adaptive 4th-Order Filter Based on Tunable N-Path Filters

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9294.pdf

**Abstract:**

This paper presents a 27.0-30.5 GHz sub-sampling PLL implemented in a 0.18um SiGe BiCMOS process. The PLL incorporates an improved Class-C VCO with a supply-side 2nd-harmonic common-mode resonance and a completely floating, transformer-based 3rd-harmonic differential-mode resonance. Despite the generations-old CMOS devices and their amplified penalty at higher frequencies, the prototype achieves sub-50fs RMS jitter at 30GHz when integrated from 1kHz to 100MHz offsets, outperforming recent state-of-the-arts in advanced CMOS nodes with similar output frequencies. The PLL achieves an excellent jitter FoM of -247.8dB when the FLL is turned on and -250.4dB when off.

A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18μm SiGe BiCMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9038.pdf

**Abstract:**

Apart from the well-known nonlinearity-induced fixed spurs, a DDSM divider-based fractional-N frequency synthesizer can manifest spurs with time-varying frequency offsets from the carrier; these are called wandering spurs. This paper presents experimental results for a 4.9 GHz CP-PLL fractional-N PLL featuring a modified MASH-based divider controller that implements wandering spur suppression. The synthesizer achieves a 20 dB reduction in the spectral envelope of the short-term output phase noise spectrum when compared to the standard MASH DDSM divider controller.

Experimental Verification of Wandering Spur Suppression Technique in a 4.9 GHz Fractional-N Frequency Synthesizer

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9138.pdf

**Abstract:**

An ultra-low power truly balanced frequency doubler has been demonstrated in a 110 nm CMOS technology, operating from 22 to 25 GHz with high fundamental rejection. Current-reused structure is leveraged to save power consumption, improve its fundamental rejection and symmetry of the differential outputs. The measured saturated power is 0-dBm and the best fundamental rejection is 44 dB. The frequency doubler operates under a 1.2 V supply voltage and achieves -4.2 dB conversion gain with 6 mW power consumption.

An Ultra-Low Power K Band Balanced Frequency Doubler with a Novel Current-Reused Structure

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9027.pdf

**Abstract:**

This paper presents a 53.25 GHz to 213 GHz frequency quadrupler with an output bandwidth of 15.5 GHz. In saturation the system achieves 11.8 dB of conversion gain at 2dBm of saturated output power. Consuming 92.9mW of DC power, the power-added efficiency is 1.6 %, a 28.7% against the current state of the art. Harmonic suppression greater than 30 dB over the full 3-dB-bandwidth is achieved, while the rejection at center frequency is greater than 45 dB. Being the first in its class to combine large power delivery with high conversion gain, more than doubling the state of the art, the demonstrated quadrupler qualifies for application in large-scale transceivers where high levels of local oscillator signal powers need to drive several parallel de-/ modulator stages.

A 213 GHz 2 dBm Output-Power Frequency Quadrupler with 45 dB Harmonic Suppression in 130 nm SiGe BiCMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9061.pdf

**Abstract:**

This work presents a broadband and high power D-band multiplier by 4 chain designed in a 130nm silicon-germanium (SiGe) BiCMOS technology. A single-ended 35 GHz input signal is made differential by a Marchand balun and multiplied by 4 by means of a Gilbert cell based quadrupler. The undesired harmonics are filtered out by a double section harmonic filter and, after a D-Band Marchand balun employed for differential to single conversion, amplified using a broadband 3-stage cascode amplifier. The presented circuit achieves a 3-dB bandwidth of 60 GHz, covering the entire D-band (110 GHz to 170 GHz) with a peak saturated output power of 8 dBm. A rejection of more than 40 dB has been measured for 3rd, 5th, 6th and 7th harmonics at 140 GHz. The designed circuit consumes 280mW from a 3.3V supply, resulting in a drain efficiency of 1.75%. The proposed solution shows a 43% relative bandwidth, which is, to the best of the authors’ knowledge, the largest among the up to now published silicon based D-band frequency multiplier by 4 chains.

A Broadband 110-170 GHz Frequency Multiplier by 4 Chain with 8 dBm Output Power in 130 nm BiCMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9269.pdf

**Abstract:**

We present a 2T0C IGZO based Capacitor-less memory that enhances the sensing margin and retention time for DRAM applications requiring higher data immunity. In the proposed technique for increased data integrity, the Read Bit-Line (RBL) is precharged at Half-VDD, instead of Full-VDD, to utilize the rising edge of read word line (RWL) at the beginning of read. This increases the storage node potential of the bit-cell (due to coupling between RWL and the storage node) which is otherwise degraded at write termination due to coupling of write word line (WWL) and the storage node.

Enhanced Data Integrity of In-Ga-Zn-Oxide Based Capacitor-Less 2T Memory for DRAM Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9029.pdf

**Abstract:**

A fast charge loss during short time retention operation was observed in word-line stacked 3-D NAND flash memory, and the origin of the fast charge loss was comprehensively evaluated. Using a fast-response pulse I-V system, the fast charge loss behaviors from lateral and vertical migration of trapped charges were thoroughly investigated and measured at various program/erase levels and temperatures in solid and checkerboard pattern.

Layout-Based Evaluation of Read/Write Performance of SOT-MRAM and SOTFET-RAM

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