Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9158.pdf

**Abstract:**

This paper benchmark the intrinsic trade-off between two essential modules of gate-all-around GAA nanosheet (NS)FETs viz. inner-spacers (ISPs) epi-induced stress in the channel. While having both ISPs and the stress is the best-case scenario for NSFET, it comes with enhanced process challenges and performance risks: poor epi-quality resulting in a no-channel stress scenario. While inner-spacers are important to parasitic capacitance reduction, we show that having intrinsic epi-stress is more beneficial and provides a better performance trade-off. We further evaluate the impact of inner-spacer κ-value and enhanced epi-volume for the two different cases. Finally, we have performed self-heating studies to show how skipping inner spacers can provide additional reduction in peak temperature.

ESSCIRC ESSDERC 2021

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-Spacers and Epi-Induced Stress: Understanding &amp; Mitigating Process Risks

inner-spacers

nanosheet

gate-all-around

stress

#### Welcome to the 62nd IEEE International Reliability Physics Symposium (IRPS)! 
**The 2024 IEEE International Reliability Physics Symposium (IRPS) was held in Dallas, Texas from April 14 to 18, 2024.** 

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**IRPS 2024 General Chair Welcome Message**

On behalf of the Management Committee of the IEEE International Reliability Physics Symposium (IRPS) and the IRPS Board of Directors, it gives me great pleasure to extend a warm welcome to all who are planning to attend the IRPS 2024, scheduled to take place from April 14-18, 2024, in Dallas, TX. 
Over its 62-year history, IRPS has solidified its position as the premiere conference for engineers and scientists to present new and original work in the field of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and other parts of the world, IRPS aims to deepen our understanding of reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS offers diverse opportunities for attendees to enhance their knowledge and understanding of all aspects of microelectronics reliability. It is also an outstanding chance to meet and network with reliability colleagues from around the world.

The IRPS 2024 technical activities will begin with two days of a total of twenty tutorial sessions covering a broad spectrum of emerging reliability topics beyond CMOS device, circuit and system reliability. These sessions are devoted to both newcomers as well as experts. Three reliability Year in Review (YIR) talks focusing on neuromorphic computing, dielectric breakdown in leading edge devices, and GaN technology will be provided on Monday after the tutorials.

The IRPS 2024 technical program will feature four distinguished keynote talks in the plenary sessions delivered by Prof. Shinichi Takagi from The University of Tokyo and Dr. Su Jin Ahn from Samsung on Tuesday, Dr. Rajeev Malik from IBM on Wednesday, and Dr. Sameer Pendharkar from Texas Instruments on Thursday. The technical program, organized into three parallel tracks, consists of contributed and seventeen invited papers from leaders in industry and academia. Additionally, two invited talks by recipients of paper awards from our sister conferences, European Symposium on Reliability of Electron Device Failure Physics and Analysis (ESREF) 2023 and the International Integrated Reliability Workshop (IIRW) 2023, will be given in the technical program. 

Tuesday evening will host ten workshops, offering an opportunity for in-depth, face-to-face discussions on emerging reliability challenges, including the three IRPS 2024 focus topics. A poster session will be held in the Austin Ranch outside the symposium building on Wednesday evening. Both events are sure to be lively. The IRPS 2024 and the International ESD Workshop (IEW) will be co-hosted with IEW registrants participating in both IRPS and IEW programs.

The IRPS 2024 will adopt a hybrid conference style, allowing virtual access to live oral presentations hosted by the Underline. Real-time streaming of all technical events (excluding Workshops and Posters) will be available in the US Central Timezone, providing virtual attendees with Q&A opportunities. For those virtual attendees who cannot watch the live presentations, the material will be available on demand to all attendees after the symposium. All authors will be presenting in person.

Finally, I would like to extend my extreme gratitude to our patrons, exhibitors, and all participants for their invaluable support, which makes IRPS successful. 

Please enjoy the IRPS 2024!

Koji Eriguchi, General Chair 
of 2024 IRPS Management Committee
 
**About IRPS** 
The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. Drawing participants from the United States, Europe, Asia, and all parts of the world, IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. IRPS provides numerous opportunities for attendees to increase their knowledge and understanding of all aspects of microelectronics reliability, and to meet and network with reliability colleagues from around the world.

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IRPS 2024 Main Conference

The IEEE International Reliability Physics Symposium (IRPS) is the premiere conference for engineers and scientists to present new and original work in the area of microelectronics reliability. IRPS seeks to understand the reliability of semiconductor devices, integrated circuits, and microelectronic assemblies through an improved understanding of both the physics of failure as well as the application environment. 

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-Spacers and Epi-Induced Stress: Understanding & Mitigating Process Risks

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
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To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9146558

**Abstract:**

In this paper, an ultra-broadband D-band wireless front-end receiver (RX) in 45nm CMOS SOI is proposed. It achieves a Noise Figure of 8 dB, a Gain of 16 dB, a 3 dB bandwidth of 25 GHz, and occupies a compact area of 2 mm2. To our knowledge, for the first time, the required millimeter-wave Local Oscillator signal is generated on-chip. Furthermore, 108 Gb/s data-rate is demonstrated by receiving and demodulating a signal composed of 10×2.16 GHz channels with -40 dBm average power and 64 QAM modulation. With a consumption of 200 mW from a 1-V voltage supply, the proposed RX achieves an energy efficiency of 1.8 pJ/bit

A 108 Gb/S 64-QAM CMOS D-Band Rx with Integrated Lo Generation

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178366

**Abstract:**

In this paper, an ultra-broadband D-band wireless front-end transmitter (TX) in 45 nm CMOS SOI is proposed. Based on channel bonding and 64-QAM modulation, it achieves 84.8 Gb/s data-rate by combining 8×2.16 GHz baseband channels. The eight baseband channels are aggregated at Intermediate Frequency (IF) in two sets of four channels and then up-converted to two adjacent sub-bands at D-band. The required millimeter-wave Local Oscillators (LO) are generated on-chip. The Intermediate Frequency band is 57.96 GHz to 66.66 GHz, and the considered transmission band is from 140.895 GHz to 158.265 GHz. The presented TX integrates two up-converter mixers, two power amplifiers and an on-chip power combiner in addition to the two LO generator with a total DC power consumption of 420 mW from a 1-V voltage supply, and occupies a compact active area of 2.98 mm2.

A 84.48Gb/S 64-QAM CMOS D-Band channel-Bonding Tx front-End with Integrated multi-Lo Frequency Generation

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9197.pdf

**Abstract:**

We here report a joint experimental and theoretical analysis of polarization switching in ferroelectric tunnel junctions. Our results show that the injection and trapping of charge into the ferroelectricdielectric stack has a large influence on the polarization switching. Our results are relevant to the physical understanding and to the design of the devices, and for both memory and memristor applications.

Polarization Switching and Interface Charges in BEOL Compatible Ferroelectric Tunnel Junctions

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9167.pdf

**Abstract:**

Magnetic Tunnel Junctions (MTJs) constitute thenovel memory element in STT-MRAM, which is ramping toproduction at major foundries as an eFlash replacement. MTJswitching exhibits a stochastic behaviour due to thermal fluctu-ations, which is modelled by s-LLGS and Fokker-Planck (FP)equations. This work quantifies the effect of thermal noise,and proposes and benchmarks a new formulation for MTJinitial conditions to accurately match thermal noise results fromstatistical simulation. Further, Finite Volume Method (FVM) andanalytical solvers for the FP equation are implemented andbenchmarked. To deploy an MTJ model for circuit design, itmust be calibrated against silicon data. To address this challenge,this work presents a scheme to fit MTJ parameters to a given setof measured current, switching time and error rate data points.

A Fokker-Planck Solver to Model MTJ Stochasticity

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9251.pdf

**Abstract:**

A semi-empirical model for the optical properties of SiGe alloys is proposed, based on physical considerations and the summation of Tauc-Lorentz and parametric oscillators. The key parameters of the oscillators are intuited from the optical transition and the symmetry points in the band structure. The model is fitted on extensive experimental data, for different temperatures, germanium concentrations and for both unstrained and strained on (100) Silicium wafer cases. This model can be used in optical simulation tools, in order to help the design of optoelectronic devices based on SiGe materials.

Semi-Empirical Model for Optical Properties of Si₁−xGex Alloys Accounting for Strain and Temperature

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9265.pdf

**Abstract:**

This paper presents a new method to reliably simulate the PDE and jitter for realistic 3D device simulations of SPAD devices. This method is based on the use of electric field lines to mimic the carriers\' trajectories, which allows the transformation of a 3D problem into a multitude of 1D problems. This idea is applied to the McIntyre model for breakdown avalanche probability to calculate PDE, but also for jitter prediction using a dedicated advection-diffusion model. The results obtained numerically are compared with an extensive series of measurements and show a good agreement on a wide variety of device designs.

Comprehensive Modeling and Characterization of Photon Detection Efficiency and Jitter in Advanced SPAD Devices

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9213.pdf

**Abstract:**

In this work, a wafer-scale fabrication of biologically sensitive Si nanowire FET is demonstrated for pH sensing and electrical detection of DNA hybridization. Based on conventional “top-down” CMOS compatible technology, our bioFETs explore a wide range of design (nanowires (NW), nanoribbons (NR), and honeycomb (HC) structures) with opening access scaled down to only 120 nm. After device fabrication, IDS-VBG transfer and IDS-VDS output characteristics show a conventional n-type FET behavior with an ION/IOFF value higher than 105, as well as an increase of threshold voltage (VTH) as the NW width is reduced. Then, using a capacitive coupling in our dual-gated Si bioFETs, the pH sensitivity is enhanced with a pH response up to 600 mV/pH. Finally, the increase of threshold voltage of n-type SiNWs due to the hybridized target DNA molecules is successfully detected

Wafer-Scale Fabrication of Biologically Sensitive Si Nanowire FET: From pH Sensing to Electrical Detection of DNA Hybridization

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9258.pdf

**Abstract:**

A CMOS industry compatible integrated resonant SiN gyroscope was fabricated with the STMicroelectronics 300 mm Photonic R&D platform. For the first time, both active Si&Ge components and low loss SiN resonant ring are integrated in an optical gyroscope, based on a ring resonator coupled to a Mach-Zehnder Interferometer. Modeling of the shot noise resolution of our device is given, resulting in a resolution of 1.08deg/s. Experimental measurement show a static gain in sensitivity of 56% compared to a single ring with the same footprint.

Design and Fabrication of a Ring-Coupled Mach-Zehnder Interferometer Gyroscope

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9287.pdf

**Abstract:**

In this work we propose and experimentally validate a relaxation oscillator architecture with ultra-high tuning range (higher than 400%, from 5KHz to more than 25kHz when the control voltage is varied from 2.5 to 5V) that exploits the reversible metal-insulator transition in 2-terminal Vanadium Dioxide thin film devices loaded to a MOSFET common source amplifier. We propose and validate an analytical model that connects key output signal metrics to the intrinsic properties of the phase-change VO2 device employed. In addition, we demonstrate RF and optical sensing capabilities, with sensitivities of 4.64 Hz/dBm and 4.23 Hz/mW to RF and Optical Power, respectively.

High Tuning Range Spiking 1R-1T VO2 Voltage-Controlled Oscillator for Integrated RF and Optical Sensing

"**Please read the paper on the following link:**

https://1worldcontent.com/ess/9226.pdf

**Abstract:**

Spin-Transfer Torque Magnetic Tunnel Junctions (STT-MTJ) are devices featuring stochastic properties. They are promising candidates for non-volatile memory or true random number generators. To design reliable hybrid CMOS circuits including STT-MTJs, one needs to use a compact model accounting for its stochasticity in the circuit simulations. This paper proposes a compact model that accurately mimics the MTJ stochastic switching behavior and meets the needs of fast execution time. The relevance of such a model together with its fast execution velocity are illustrated with a bitstream generator.

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A 108 Gb/S 64-QAM CMOS D-Band Rx with Integrated Lo Generation

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Next from ESSCIRC ESSDERC 2021

A 108 Gb/S 64-QAM CMOS D-Band Rx with Integrated Lo Generation

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Challenges of gate stack TDDB in gate-all-around nanosheet towards further scaling

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PRESENTATIONS

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