VIDEO DOI: https://doi.org/10.48448/7x3y-ff31

technical paper

ESSCIRC ESSDERC 2021

September 14, 2021

Italy

Ultrahigh-Density 3-D Vertical RRAM with Stacked Junctionless Nanowires for In-Memory-Computing Applications

Please log in to leave a comment

Downloads

SlidesPaperTranscript English (automatic)

Next from ESSCIRC ESSDERC 2021

A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI
technical paper

A 2.5-GHz Clock Recovery Circuit Based on a Back-Bias-Controlled Oscillator in 28-nm FDSOI

ESSCIRC ESSDERC 2021

+2Andreia CathelinDavid BolMaxime Schramme
Maxime Schramme and 4 other authors

14 September 2021

Similar lecture

IGZO-Based Compute Cell for Analog In- Memory Computing—DTCO Analysis to Enable Ultralow-Power Ai at Edge
technical paper

IGZO-Based Compute Cell for Analog In- Memory Computing—DTCO Analysis to Enable Ultralow-Power Ai at Edge

ESSCIRC ESSDERC 2021

+11Daisuke Saito
Daisuke Saito and 13 other authors

14 September 2021

Stay up to date with the latest Underline news!

Select topic of interest (you can select more than one)

PRESENTATIONS

  • All Lectures
  • For Librarians
  • Resource Center
  • Free Trial
Underline Science, Inc.
1216 Broadway, 2nd Floor, New York, NY 10001, USA

© 2023 Underline - All rights reserved