Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9134399

**Abstract:**

This paper describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-interleaved ADC (TI-ADC), clock generation, clock distribution, feed-forward equalizer (FFE), decision feedback equalizer (DFE), and calibration. The TI-ADC is implemented as a 56–67-GSa/s, 36-way arrangement of dualcomparator SAR ADCs (SAR subADCs). The Rx achieves BER better than 1e-4 for a data rate as high as 127 Gb/s, with 3.2e-4 BER at 134.4 Gb/s, over a 15-dB die-to-die loss channel and achieves 3e-6 BER over a 33-dB die-to-die channel loss at 28-GHz Nyquist while consuming 5.1 pJ/b of power, excluding DSP power.

ESSCIRC ESSDERC 2021

A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

time interleaved sar adc

wirelines receiver

pam4

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9200.pdf

**Abstract:**

This work presents an SRAM macro for continuous data buffering, simultaneous (always-on) in-memory computing for area- and energy-efficient event detection, and energy-efficient bulk read upon event occurrence for off-memory deeper data insights. The bitcell with non-precharged operation enables signed current summing for energy-efficient inference, 90% bitline activity reduction in conventional reads without any data prediction circuitry. Hence, the proposed SRAM uniquely enhances energy efficiency both in read access and in-memory compute operation. The proposed SRAM achieves 109TOPS/mm2 area efficiency and 749-1,459TOPS/W energy efficiency in 28nm under neural net workloads.

SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-on Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9198.pdf

**Abstract:**

This paper presents a reconfigurable in-memory computing macro for processing neural networks using 7T SRAM bitcells with decoupled read with an extra NMOS transistor. Zero inputs and weights are skipped based on the dual bitcell structure for saving energy. Binary-searching ADCs are embedded into every columns of the bitcell array and they enhance the performance and energy-efficiency. There are three types of bitcells per each bitcell column for processing dot-products, calibrating offsets, and performing a binary-searching ADC operation column-by-column. A test-chip is fabricated using 65nm, and the linearity of 128x column-based neurons are measured.

A Zero-Skipping Reconfigurable SRAM In-Memory Computing Macro with Binary-Searching ADC

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9179.pdf

**Abstract:**

This paper presents a buck converter with sub-nW quiescent power, high efficiency, and a wide dynamic range for ultra-low-power (ULP) IoT SoCs. To optimize the SoC power consumption, the buck converter supports fast dynamic voltage and frequency scaling (DVFS) and enables fast load-transient response (FLTR) through asynchronous control. In addition, the buck converter is fully self-contained with all features integrated on chip including a proposed adaptive deadtime controller. Fabricated in 65nm CMOS, measurement results show the buck converter has an 802pW quiescent power at 1.5V input voltage and a 93% peak efficiency. The measured dynamic range is from 0.5nW to 2.75mW, which is over 6 orders of magnitude. The measured voltage droop is 54mV for a 45nA-to-1mA load current step thanks to the asynchronous load-transient detector. The buck converter achieves the highest efficiency and widest dynamic range among all the state-of-the-art sub-nW switching voltage regulators, which makes it well suited for power management in ULP SoCs.

An 802pW 93% Peak Efficiency Buck Converter with 5.5×106 Dynamic Range Featuring Fast DVFS and Asynchronous Load-Transient Control

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9130.pdf

**Abstract:**

This work presents a fast-transient and low-power, external-clock-less digital low-dropout regulator (DLDO) using a wide-range adaptive sampling frequency, fSP. Using two tightly-interlocking sub-comparators, i.e., a delay-line-based comparator (DLC) and an edge-racing comparator (ERC), the proposed gear-shifting comparator (GSC) can scale the fSP dynamically in a wide range so that it can make the DLDO concurrently achieve a fast response in the transient state and a small quiescent current in the steady state. Fabricated in a 65-nm CMOS process, the DLDO achieved a 46-ns settling time using only a 10-μA quiescent current. The transient FOM was 0.0084 mV, which was the best among the state-of-the-art DLDOs.

A 0.0084-mV-FOM, Fast-Transient and Low-Power External-Clock-Less Digital LDO Using a Gear-Shifting Comparator for the Wide-Range Adaptive Sampling Frequency

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9142.pdf

**Abstract:**

This paper proposed a light-load efficient DC-DC converter with dual-lower-bound hysteresis control and frequency control for always-on Internet-of-Things applications. The dual-lower-bound hysteresis control allows the frequency to change dynamically according to the load current, which enhances the light-load efficiency. A fast transient response is also provided for wake-up events in IoT devices. A fully integrated 1/2 capacitive DC-DC converter is implemented in 180 nm CMOS process to demonstrate this concept. The result shows that a 77.3% efficiency is guaranteed over 100x load current ranges and a 80 ns active response time is achieved in 0.04 mA - 4 mA load transient.

A Switched-Capacitor DC-DC Converter with >77.3% Efficiency and 80 Ns Active Transient Response in 40 μA - 4 mA Load Current Range

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9127.pdf

**Abstract:**

A fully integrated ultra-low-power step-down DC-DC converter is demonstrated in 65nm. This circuit is useful for converting battery voltage levels (2.5 - 3V) to digital and mixed-signal voltage levels for low-power always-on domains. A down conversion of 5:1 is utilized to provide a near-Vth digital voltage of 0.55-0.6V, while making higher voltages (1.2V, 1.8V) available as well. An inverter-based amplifier is utilized to achieve high speed regulation at low power. Measured results show an Efficiency-Enhancement-Factor (EEF) of 66% and a power density of 2.56 mW/mm2 at an output power of 100μW, which are state-of-the-art properties at this power level.

An Inverter-Based, Ultra-Low Power, Fully Integrated, Switched-Capacitor DC-DC Buck Converter

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9169677

**Abstract:**

This letter presents a wireless transmitter (TX) front end in which the functionalities of digital-to-analog conversion, baseband filtering, and signal upconversion are implemented by a passive switched-capacitor (PSC) network. The result is a versatile architecture that fully benefits from CMOS scaling. The front end was integrated in a 65-nm CMOS technology and can support various channel bandwidths simply by adjusting the switching frequency for the PSC network. Thanks to its third-order reconfigurable filter, it maintains a thermal noise floor better than -156 dBc/Hz at a power dissipation of 45 mW. The measured prototype achieves an ACLR2 of -57 dB and an EVM of -31 dB for a 20-MHz 64-QAM OFDM and a 20-MHz 16-QAM signal, respectively.

A Reconfigurable Passive Switched-Capacitor TX RF Front End with −57 dB ACLR2

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9152038

**Abstract:**

True-time-delays enable wideband analog and hybrid beamforming by mitigating the beam squint problem. This paper reports a true-time-delay beamforming receiver supporting delays up to three carrier-frequency cycles. The inherent delay scaling with frequency enables true-time-delays for large arrays at low-GHz frequencies where long delays are required due to lambda/2 antenna spacing. The delays are implemented through delayed resampling of a passive mixer\'s discrete-time output. Driving the mixers with pulse-skipped local oscillator (LO) signals allows the delay range to exceed one carrier cycle.A polyphase receiver structure prevents aliasing of noise and unwanted tones caused by LO pulse-skipping.

A 0.6–4.0 GHz RF-Resampling Beamforming Receiver with Frequency-Scaling True-Time-Delays Up to Three Carrier Cycles

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9144258

**Abstract:**

A TX power calibration loop with high accuracy for millimeter-Wave (mm-Wave) automotive radar application is presented. The loop consists of a calibration logic, a variable gain amplifier (VGA), a power amplifier, a power detector, an analogue-to-digital convertor (ADC) and a temperature sensor fabricated in a 40 nm CMOS process. The digital power calibration loop is implemented to adjust the monitored detector output voltage to a predetermined target voltage according to a temperature by controlling the gain of the VGA. To achieve high power accuracy and stability against temperature variation, the proposed power detector is designed to realize flat or monotonic characteristics against temperatures by optimizing a second distortion. Measured calibrated output power shows 10 dBm ±0.5 dB over wide temperatures ranging from −20˚C to 125˚C.

Power Calibration Loop with High Accuracy of 10 dBm ±0.5 dB for a 77-GHz Radar Application

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9187850

**Abstract:**

A 280-GHz, fully integrated and digitally controlled multiport coherent radiator is presented. The silicon die acts as a chip-scale dielectric resonator antenna (CSDRA) and is excited by four differential loop inductors. The chip incorporates a balun for an X-band input signal, a 1-4 ultracompact differential Wilkinson splitter, and four ×27 active multipliers chain (AMC), which drive the four exciting elements. Highresolution, digitally controlled true time delay (TTD) elements, based on digitally controlled artificial dielectric transmission lines (DiCAD), are used to calibrate the variations between channels to optimize overall broadside radiated power and enable beam steering of ±15°. High-resolution DACs are used to accurately set the bias through a 3-wire SPI module. Fabricated in 65-nm CMOS, the 1.4×2-mm 2 chip achieves a record EIRP of +21 dBm, a TRP of +8.5 dBm, and a power density of 2.25 mW/mm 2 with 0.72% total efficiency, without using any external lens, superstrate, or postprocessing.

A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

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SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-on Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm

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A 112–134-Gb/S PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

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Next from ESSCIRC ESSDERC 2021

SRAM with In-Memory Inference and 90% Bitline Activity Reduction for Always-on Sensing with 109 TOPS/mm2 and 749-1,459 TOPS/W in 28nm

Similar lecture

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads