Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9319.pdf

**Abstract:**

Today several speculative visions are conjecturing on what 6G will be able to offer. Nevertheless, the 6G design process is at its preliminary stages. Reality today is that hardware, technologies and new materials required to effectively meet performance targets, have not been designed, tested or even do not exist yet. The contribution of this paper is three-fold. We derive crucial 6G key performance indicators on hardware and technology design. We present a new technology design methodology for effective software-hardware components integration. Third, we suggest a paradigm shift towards goal-oriented and semantic communications. Our recent results consolidate the proposed vision.

ESSCIRC ESSDERC 2021

Toward 6G: From New Hardware Design to Wireless Semantic and Goal-Oriented Communication Paradigms

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9170.pdf

**Abstract:**

A compact analytical model is reported capturing the effects of Coulomb Blockade and charge quantization on the drain current characteristics of a MOSFET-based semiconductor quantum dot at cryogenic temperatures. It is implemented as a Verilog-A add-on to the foundry-provided MOSFET model to facilitate potential integration in any design kit and allow for simulation of quantum processors that integrate qubits and control electronics on the same die. The model was verified in the 6-50 K temperature range on the measured I-V characteristics of a nanoscale p-MOSFET fabricated in production 22nm FDSOI CMOS technology.

Compact Modelling of 22nm FDSOI CMOS Semiconductor Quantum Dot Cryogenic I-V Characteristics

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9050.pdf

**Abstract:**

In this paper, we propose a fully integrated area-efficient bias generation system using a single input reference for a 2D quantum core structure comprising quantum dot arrays. The arrangement of biases initializes the quantum structure before a sophisticated quantum experiment can commence. The circuit area is 0.011mm^2 and the power consumption is 220uW at 3.5K with a 0.8V supply in a 22nm FD-SOI process. The proposed scheme can be readily extended to more complex quantum structures.

Bias Generation and Calibration of CMOS Charge Qubits at 3.5Kelvin in 22-nm FDSOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9302.pdf

**Abstract:**

A novel coherent optical link is proposed to serve as the interconnection technology between the room temperature and cryogenic temperature environment for quantum computing and high-performance superconducting computing. The trade-off on the energy efficiency of this link is discussed. A prototype optical transmitter is fabricated in the 45RFSOI CMOS process and characterized at the cryogenic temperature. Measurement results show that this optical transmitter is able to be directly driven by superconducting electronics with millivolt-level voltage swing, and the new link has five times better energy efficiency than the traditional intensity modulation, direct-detection link.

Electronic-Photonic Cryogenic Egress Link

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9068.pdf

**Abstract:**

Digital PLLs are nowadays recognized as a viable approach for the design of high-performance frequency synthesizers in scaled CMOS technologies. Latest implementations allow achieving at low power both state-of-the-art rms jitter, between 50fs and 100fs, and highly linear fast frequency modulation capability, thus enabling both high-efficiency communications systems and radar applications in CMOS. This paper will briefly trace the path from the (re-)discover of this approach to the more recent solutions, discussing the main characteristics of key building blocks and their limitations such as the non-linearities, and the noise, that still calls for a sound knowledge of analog design techniques.

Digital PLLs: the Modern Timing Reference for Radar and Communication Systems

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9322.pdf

**Abstract:**

We examine the potential design and performance of 100-300 GHz wireless communications systems, examine the required transistors performance, and describe our present efforts to develop InP bipolar and field-effect transistors to serve in the transmitters and receivers of such systems .

Transistors for 100-300GHz Wireless

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9013.pdf

**Abstract:**

This work introduces a neuromorphic chip featuring energy-efficient transfer learning capability using a new learning rule, Delta- Spike Time Dependent Plasticity (STDP). Delta STDP enables the neuromorphic chip to leverage on its previous knowledge to learn and to solve different but related tasks at a faster rate and with a limited number (few shots) of training samples. Compared to the unsupervised on-chip learning (OCL) rules, Delta STDP offers lower learning overheads as it has ~20% lower memory utilization and is operated only on the last layer of the Spiking Neural Network (SNN). A test chip fabricated in 40nm demonstrates this on-chip learning concept using DVS gesture and MNIST datasets. It achieves an accuracy of >80% for DVS gesture (using 9.8K training samples) with the total energy/learning is 5.2J at 0.5V. For MNIST, using only 2K training samples, it attains an accuracy of 97% and this learning convergence rate is >10x the conventional OCLs. The total energy/learning for MNIST dataset is 8.6mJ at 0.5V. Overall, the chip consumes 2.1 pJ/SOP at 0.5V, which is 12.3x-91.4x lower compared to the existing state-of-the-art.

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-Chip Transfer Learning Using Delta STDP

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9296.pdf

**Abstract:**

We propose an always-on keyword spotting chip with an acoustic activity detection (AAD). Extracted from feature extractor, this AAD has zero overhead and zero miss rate. We also propose a tunable detection window to fit keywords with different widths to get better accuracy. Besides, a non-overlapping-frame Mel frequency cepstrum coefficient is used in the KWS system to reduce memory footprint and processing cycles. Implemented in a 28nm CMOS technology, its power consumption is only 0.36μW for AAD and 0.8μW for KWS at 0.4V. And MFCC circuit has only 170nW power consumption. The accuracy can reach 97.8% for two keywords.

AAD-KWS: A Sub-µW Keyword Spotting Chip with a Zero-Cost, Acoustic Activity Detector from a 170nW MFCC Feature Extractor in 28nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9261.pdf

**Abstract:**

This work presents the first on-chip, mixed-signal echo state network (ESN) for the early prediction of heart disease. The ESN comprises an input layer, a non-linear projection (NP) layer, and an output layer. Only the output layer of the ESN requires training. The input layer weights are time-invariant and drawn from a static binary random distribution. Thus, the proposed ESN has significantly lower trainable parameters than other non-linear neural networks used for similar prediction tasks. A 65nm prototype is validated with the Cleveland Heart Disease (CHD) dataset. The ESN achieves a mean accuracy of 84.6% over 5 test chips while consuming 7.5nJ energy/inference.

7.5nJ/Inference CMOS Echo State Network for Coronary Heart Disease Prediction

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9045.pdf

**Abstract:**

This work presents a FloatSD8-based system on chip (SOC) for the inference as well as the training of a convolutional neural networks (CNNs). A novel number format (FloatSD8) is employed to reduce the computational complexity of the convolution circuit. By co-designing data representation and circuit, we demonstrate that the AISOC can achieve high convolution performance and optimal energy efficiency without sacrificing the quality of training. At its normal operating condition (200MHz), the AISOC prototype is capable of 0.69 TFLOPS peak performance and 1.625 TOPS/W in 28nm CMOS.

A 1.625 TOPS/W SOC for Deep CNN Training and Inference in 28nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9047.pdf

**Abstract:**

Distributed smart sensors are more and more used in applications such as biomedical or domestic monitoring. However, each sensor broadcasts data wirelessly to the others or to an aggregator, which leads to energy-hungry sensor nodes and an increased latency at the network level. To tackle both challenges, this work proposes to distribute part of the processing elements in each sensor node and presents a 28nm FDSOI ASIC implementation of an associative memory using clique-based neural networks (CBNNs) coupled with an integrated SRAM memory. It consumes 43pJ for a single inference, which is 6.5 times better than state-of-the-art associative memories implementations, for the same memory size.

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Next from ESSCIRC ESSDERC 2021

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A 22–31 GHz Bidirectional 5G Transceiver Front-End in 28 nm CMOS

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