Italy

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9056.pdf

**Abstract:**

RRAM-based compute-in-memory (CIM) has shown great potentials for deep neural network inference. Prior works generally used off-chip write-verify for tightening resistance distributions and off-chip ADC references to fine-tune partial sum quantization, which may be unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate ADC offsets to guarantee CIFAR-10 accuracy of &gt;90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W on VGG-8 network.

ESSCIRC ESSDERC 2021

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

adc reference generation

write-verify

compute-in-memory

rram

non-volatile memory

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Please read the paper on the following link:**

https://1worldcontent.com/ess/9056.pdf

**Abstract:**

RRAM-based compute-in-memory (CIM) has shown great potentials for deep neural network inference. Prior works generally used off-chip write-verify for tightening resistance distributions and off-chip ADC references to fine-tune partial sum quantization, which may be unsuitable for practical applications. This work presents an RRAM-CIM macro that features 1) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift, and 2) on-chip ADC reference generation that provides column-wise tunability to mitigate ADC offsets to guarantee CIFAR-10 accuracy of >90%. The design is taped-out in TSMC N40 RRAM process, and achieves 36.4TOPS/W on VGG-8 network.

technical paper

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9129816

**Abstract:**

Active rectifier, biomedical implantable devices, coarsefine, delay compensation, wireless power transfer (WPT). This letter presents an active rectiﬁer with SAR-assisted coarse-ﬁne adaptive digital delay compensation technique for biomedical implantable devices. Both on- and off-delays are compensated by adjusting the comparator offset. In order to achieve accurate zero-voltage switching against process, voltage, and temperature variations, a two-step coarse-ﬁne digital tuning method is introduced. The coarse-tuning phase and the ﬁne-tuning phase are controlled by a 7-bit SAR controller and a 3-bit bidirectional counter, respectively. The proposed technique could avoid reverse current and achieve maximum conduction time for power switches. Meanwhile, it is suitable for compensating power switch with large on/off-delay variation.

A 13.56-MHz Active Rectifier with SAR-Assisted Coarse-Fine Adaptive Digital Delay Compensation for Biomedical Implantable Devices

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9152041

**Abstract:**

A multichannel impedance-sensing CMOS chip for the readout of non-invasive light detectors in Silicon Photonics is presented. The performance of the lock-in phase-sensitive demodulator is improved thanks to a capacitive feedback transimpedance amplifier (TIA) equipped with an active discharge network, able to keep a DC output offset lower than 3 mV for leakage currents up to 4 nA while injecting a noise lower than 40 fA/sqrt(Hz). The addition of a sensor capacitance compensation system at the input of the chip allows a 30-fold increase of the stimulation amplitude, enabling the tracking of sub-picoSiemens conductance variations on a baseline of few uS, with a bandwidth of 70 Hz. The chip performance opens the way to multipoint monitoring of complex photonic systems, addressing the challenges posed by the growing complexity of these architectures.

Wide Dynamic Range Multichannel Lock-in Amplifier for Contactless Optical Sensors with Sub-Ps Resolution

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9023.pdf

**Abstract:**

This paper focuses on the comparison of various advanced substrates such as trap-rich (TR), porous silicon (PSi), gold-doped (Au-Si) and smart-implants PN-junction (DP) in terms of RF performances. Both small- and large-signal measurements were performed, including the study of the influence of temperature and bias voltage. The purpose of this paper is to provide an overview of the characteristics of these multiple substrates to facilitate design choices for RF-IC applications.

High-Temperature Characterization of Novel Silicon-Based Substrate Solutions for RF-IC Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9292.pdf

**Abstract:**

This paper presents dual-layer proton irradiation profile to improve the thermal stability of high-resistivity substrate formed by low-fluence proton irradiation. Dual-layer irradiation uses targeted irradiation to the Si-SiO2 interface to reduce the fluence required for preventing the formation of conduction layer after annealing. Thermal stability of effective substrate resistivity is evaluated indirectly through inductor Q-factor measurement before and after annealing at 260°C for 1 minute. With the same total fluence, measurement result shows the proposed dual-layer irradiation profile can suppress post-anneal Q-factor degradation from 17% to 1%. The required active devices margin from irradiated area is also reduced by 26%.

Dual-Layer Proton Irradiation for Creating Thermally-Stable High-Resistivity Region in Si CMOS Substrate

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9117.pdf

**Abstract:**

Shunt admittance of FETs for mm-wave switch applications are investigated, complementing the well-know series elements Ron/Coff. Tese shunt elements can be responsible for significant loss, and devices with the lowest RonCoff may not be the best suited for high-frequency switches. This is demonstrated by comparing 20 nm SLVT and BFMOAT devices from GLOBALFOUNDRIES’ 22FDX® technology. While the SLVT presents an RonCoff metric of 100 fs, it is outperformed by the BFMOAT that has an RonCoff of 160 fs, thanks to reduced parasitic shunt loss. A DC-80 GHz SPDT is measured, showcasing BFMOAT’s excellent characteristics for mm-wave switches, achieving competitive results.

Impact of Device Shunt Loss on DC-80 GHz SPDT in 22 nm FD-SOI

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9040.pdf

**Abstract:**

The adoption of 5G mmWave is upon us, with major cell phone companies having introduced phones with mmWave capabilities and major US cellphone providers building their infrastructure out. Parts manufactured using Globalfoundries 45RFSOI technology have made significant traction in the infrastructure space. A good part of the success of this technology is based on the excellent high frequency performance of the thin oxide device, the high resistivity substrate and the high voltage support enabled by the use of stacking in SOI technologies. In this paper we introduce a new transistor developed to improve the output power of mmWave power amplifiers (PA). It demonstrates ~ 1.2X increase in maximum voltage, reduced linear mode resistance and ~20% increases in fMAX to >400 GHz

Novel mmWave NMOS Device for High Pout mmWave Power Amplifiers in 45RFSOI

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9131838

**Abstract:**

This paper presents the first GC-eDRAM in 16nm FinFET technology, featuring a mixed-VT 3T gain-cell structure to minimize the storage node (SN) leakage. The implemented 1 Mbit 3T GC-eDRAM is fully logic-compatible and provides a 2X smaller bitcell size compared to a 6T SRAM with similar design rules, offering the highest density logic-compatible memory cell in 16nm technology. Measurement results demonstrate a 77 μs DRT under a 600mV VDD, which is over 10X longer than previously reported GC-eDRAMs in 28nm technologies. The memory was fully operational at temperatures spanning -40C–125C and under a supply voltage as low as 450mV, providing the lowest measured VDDmin and widest temperature range reported in the literature for GC-eDRAM.

A 1 Mbit Fully Logic-Compatible 3T Gain-Cell Embedded DRAM in 16nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9187832

**Abstract:**

An area-efficient inductive coupling interface for a 3-D-stacked high-bandwidth memory is presented. A test chip was fabricated in a 40-nm CMOS technology and 1.5-Gb/s 2.2-pJ/bit communication using a 0.23-V NMOS transmitter and 7-µm multi-layer coils was experimentally confirmed. The low-voltage transmitter reduces power dissipation by 55% in measurement. The proposed 7-µm multi-layer coils improve their mutual inductance by a factor of 4.5 compared with conventional single-layer ones. Using this interface, a memory module consisting of eight 8-µm-thick memory dies and a base die in a 40-nm CMOS process is extrapolated to achieve a 2.3-Tbps/mm2 area efficiency and 6.1-pJ/bit energy efficiency.

Area-Efficient Multi-Hop Inductive Coupling Interface for 3D-Stacked Memory with 0.23-V Transmitter and Sub-10-μm Coil Design

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9158520

**Abstract:**

We proposed 3D-based redundancy scheme for stacked DRAM systems, which enables high productivity with wafer-on-wafer (WOW) technology. Vertically replaceable block scheme, and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both of the WOW technology and the leading-edge technologies, is dealt with in this study. Evaluation of many layers stacking capability leads to the result, that 3D redundancy technique is applicable even for devices with many layers of stacking. Therefore, this technique makes the WOW technology, as another system scaling enabler.

Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9154.pdf

**Abstract:**

We demonstrate the first MRAM-based IMC macro, implemented in an advanced-node 22nm FD-SOI technology from GF and achieving high row parallelism, for maximizing IMC gains. Our implementation is enabled by high-sensitivity pitch-matched readout circuits, addressing non-idealities using both circuit and software techniques. We present basic operation and neural-network (NN) CIFAR-10 classification, leveraging a generalized training algorithm and achieving 5.1 TOPS/W and 758 GOPS/mm2.

A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

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Next from ESSCIRC ESSDERC 2021

A 13.56-MHz Active Rectifier with SAR-Assisted Coarse-Fine Adaptive Digital Delay Compensation for Biomedical Implantable Devices

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A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References

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Next from ESSCIRC ESSDERC 2021

A 13.56-MHz Active Rectifier with SAR-Assisted Coarse-Fine Adaptive Digital Delay Compensation for Biomedical Implantable Devices

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A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area

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