Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9129800

**Abstract:**

A CMOS Voltage Level Detector (VLD) circuit is proposed for IoT systems which operates near the minimum energy point. It can accurately detect VCC levels of 550-640mV, making it one of the lowest voltage VLDs reported to date. A novel pull-up circuit is utilized to accurately detect fast VCC ramps of 10’s of micro seconds, which are faster than the power-up of the VLD itself. This feature enables it to operate at a low power consumption of 2.6uW. A low voltage, charge-pumped bandgap reference is utilized with a highly accurate comparator to achieve a 35mV variation across temperature and a random variation sigma of 1.68mV. This circuit is one of the lowest voltage, most highly accurate and fastest ramp-detect VLDs that have been reported in the literature.

ESSCIRC ESSDERC 2021

An Accurate 0.55V 2.6 µW Voltage Level Detector

voltage-level detector (vld)

power-good

power management

bandgap

cmos

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

This letter presents a RISC-V System-on-Chip (SoC) with fully integrated switched-capacitor DC–DC converters, adaptive clock generators, mixed-precision floating-point vector accelerators, a 5-Gb/s serial memory interface, and an integrated power management unit (PMU) manufactured in 28-nm FD-SOI. The vector accelerator improves performance and energy per task on a matrix multiplication kernel by 15x and 13x, respectively, and end-to-end performance on machine learning and graph analytical workloads by 8x–12x. Inclusion of microarchitectural counters and fine spatial power-domain granularity facilitate the predictive power-management algorithms that reduce energy per task by 13%–22% compared to the baseline scalar processor. System level simulations of a range of SoC architectural variations with multiple cores and vector accelerators complement the silicon measurements.

Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9146537

**Abstract:**

The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either improved performance or lower energy consumption as a function of the actual computational workload. This flexibility is demonstrated for the first time by silicon measurements on a 16 × 16 -b Booth multiplier fabricated as a part of an ultralow-power digital signal processing (DSP) architecture for 16-nm FinFET technology. When running in the full-speed mode, the DML multiplier can achieve a performance boost of 19.5% as compared to the equivalent standard CMOS design. The same circuit saves precious energy (-27%, on average) when the energy-efficient mode is enabled, while occupying 13% less silicon area.

A 0.8-V, 1.54-pJ/940-MHz Dual-Mode Logic-Based 16×16-B Booth Multiplier in 16-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9177177

**Abstract:**

A 10nm DNN inference accelerator compresses model size with tabulation hash-based fine-grained weight sharing and increases 8b-compute density by 3.4× to 1.6 TOPS/mm2. The compressed model DNN implements lightweight hashing circuits to compress fully connected and recurrent neural networks. Optimized shared weight address generation reduces MUX tree area overhead by 40%. Runtime hash table generation and weight mapping circuits enable a peak energy efficiency of 9.0TOPS/W at 450mV, 25°C. A 128×-compressed 3-layer LSTM classifies TIMIT phonemes with 85.6% accuracy for a total energy of 14µJ/classification, with <0.5% degradation in accuracy over an uncompressed network.

A 9.0TOPS/W Hash-Based Deep Neural Network Accelerator Enabling 128× Model Compression in 10nm FinFET CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9134388

**Abstract:**

A 10nm compute-near-memory (CNM) accelerator augments SRAM with multiply accumulate units (MACs) to reduce interconnect energy and achieve 2.9 8b-TOPS/W for matrix-vector computation. The CNM provides high memory bandwidth by accessing SRAM sub-arrays to enable low-latency, real-time inference in fully connected and recurrent neural networks with small mini-batch sizes. For workloads with greater arithmetic intensity such as large-batch convolutional neural networks, the CNM reconfigures into a 2D systolic array to amortize memory access energy over a greater number of computations. Variable-precision 8b/4b/2b/1b MACs increase throughput by up to 8× for binary operations at 33.0 1b-TOPS/W.

A 2.9-33.0 TOPS/W Reconfigurable 1D/2D Compute-Near-Memory Inference Accelerator in 10nm FinFET CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9153788

**Abstract:**

A processing-in-memory (PIM)-based accelerator is presented in 65-nm CMOS for on-chip learning in spiking neural network using timing-based stochastic spike-timing-dependent plasticity (STDP). The design uses mixed-signal processing in the 8T-SRAM array for spike accumulation and all-digital computation for neuron dynamics and synaptic weight updates. The 0.39-mm2 and 14.83-mW test chip demonstrates 100K images/second learning rate and 148.3 nJ/image learning energy.

Processing-In-Memory-Based On-Chip Learning with Spike-Time-Dependent Plasticity in 65-nm CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178725

**Abstract:**

This paper presents a redistributable capacitive power converter for batteryless optically-powered Internet-of-Things (IoT) devices. The proposed converter employs redistributable two-stage charge pump along with a storage capacitor to power milli-watt order low-power RF power amplifier occasionally using indoor light illumination. The first stage tracks the maximum power point of PV cell and stores the energy to the storage capacitor. The second stage further boosts the output to 1.5 V with voltage regulation. The proposed capacitive converter is composed of 16 1.5×/2× reconfigurable charge pump submodules and a digital low dropout regulator (DLDO) to adapt 0.45 to 0.9 V PV input with high efficiency. The submodules are redistributed among two stages according to operating mode to reduce 46.7% on-chip capacitors. The proposed capacitive power converter is fabricated in 0.18 μm CMOS process. The measured results demonstrate the peak power conversion efficiency is 91%, 63.8%, and 68.5% under 1×, 1.5×, and 2× conversion ratios, respectively.

A Redistributable Capacitive Power Converter for Indoor Light-Powered Batteryless IoT Devices

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9336128

**Abstract:**

Generative Adversarial Networks (GAN) consists of multiple deep neural networks cooperating and competing each other. Due to their complex architectures, training GANs requires huge computations and external memory accesses. However, retraining GANs with user-specific data is critical on mobile devices because the pretrained model outputs distorted images under user-specific conditions. This paper proposes an FPGAbased GAN training accelerator to enable energy-efficient domain specific optimization of GAN with user’s local data. A SELRET(Selective-Layer Retraining) is proposed to reduce the computation by 69% through selecting layers that are effective in enhancing the quality of the output. Moreover, ROLIN (Reordering Layers for Instance Normalization) is proposed to reduce the external memory accesses of intermediate data. The design is implemented on Intel’s Cyclone V, showing 51 GFLOPS peak performance with 10.04GFLOPS/W energy-efficiency for face modification of 256×256 image.

An Energy-Efficient GAN Accelerator with On-Chip Training for Domain Specific Optimization

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199903

**Abstract:**

In this paper, a broad-purpose compute-inmemory solution (±CIM) able to handle arbitrary sign in both inputs/features and weights/coefficients is introduced. The ability to operate on arbitrary sign and under variable precision on both operands enables a wide range of applications, ranging from conventional neural networks to digital signal processing and monitoring. The ±CIM pipelined architecture, the reconfigurable row encoder and the adoption of a commercial 2-port bitcell allow uninterrupted memory availability for conventional read/write, even when performing in-memory computations.

Broad-Purpose In-Memory Computing for Signal Monitoring and Machine Learning Workloads

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9491142

**Abstract:**

Time-domain computing-in-memory (TD-CIM) architectures have three challenges for accelerating multi-bit DNNs due to their inferior bit-split convolution: poor network adaptability, massive redundant computations, and high quantization energy and error. This work firstly proposes a unique-weight kernel decomposition based convolution method for accelerating multi-bit DNNs. Then a TD-CIM based processor is designed with three techniques to address above challenges: 1) Cross-flipping based kernel decomposer to reduce memory accesses, 2) Dual-mode complementary predictor to remove redundant computations, 3) Activation-weight-adaptive pulse quantizer to reduce quantization energy and error. Fabricated in 28nm and evaluated with 1-to-8bit DNN, the processor achieves 2.4-to-152.7TOPS/W peak energy efficiency.

A Time-Domain Computing-in-Memory Based Processor Using Predictable Decomposed Convolution for Arbitrary Quantized DNNs

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9203868

**Abstract:**

A 6.4 nW 1.7 % relative inaccuracy (R-IA) CMOS sub-thermal drain voltage-based temperature sensor is proposed. The proposed stabilized sub-thermal drain voltage current generator achieves a highly linear PTAT output without nonlinearity fitting or post-fabrication trimming, and increases the accuracy of the sensor. The combination of the current generator and a frequency-locked-loop relaxes the tradeoff between power and temperature stability of the current-to-frequency converter, and achieves supply-voltage-independent operation. Measured results of the prototype fabricated in a 65 nm CMOS process show that the proposed temperature sensor has a -1.0/+0.7 °C inaccuracy (= R-IA of 1.7 %) while achieving a resolution of 75 mK over a temperature range of -30 to 70 °C. The line sensitivity of the sensor is 2.8 °C/V.

An Accurate 0.55V 2.6 µW Voltage Level Detector

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Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI

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A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency Locked Loop

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An Accurate 0.55V 2.6 µW Voltage Level Detector

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Next from ESSCIRC ESSDERC 2021

Programmable Fine-Grained Power Management and System Analysis of RISC-V Vector Processors in 28-nm FD-SOI

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A 6.4 nW 1.7% Relative Inaccuracy CMOS Temperature Sensor Utilizing Sub-Thermal Drain Voltage Stabilization and Frequency Locked Loop

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COMPANY

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