United States

Abstract Body: Gallium nitride (GaN) has been considered as a promising candidate for power electronic devices due to its wide bandgap (3.4 eV), high critical electric field (3 MV/cm), and high electron mobility (&gt;1000 cm2/V s). As a key parameter to evaluate the performance of power devices, Baliga’s figure of merit (BFOM) of GaN is more than 500X higher than silicon (Si) and 3X higher than silicon carbide (SiC) [1]. Vertical GaN PN diode with 5kV breakdown voltage (VBR) has been demonstrated [2]. Although tremendous progress has been made in the past few years, achieving vertical GaN power devices with VBR of 10-20 kV remains challenging. Epitaxy of high-quality GaN films with a thick drift layer, low controllable doping, and high mobility is required to advance the field. In this work, the effects of increasing GaN growth rate on the impurity incorporation, charge compensation, surface morphology, and transport properties are systematically studied. Under optimized MOCVD GaN growth condition, high-quality GaN films with controllable low net charge concentration (Nd-Na) at 4×1015 cm-3 was demonstrated. Secondary ion mass spectroscopy (SIMS) measured [Si] and Nd-Na as a function of SiH4 flow rate was investigated. The compensation level at (4.8±1.0)×1015 cm-3 was extracted from the intercept of Nd-Na vs. SiH4 flow rate. Based on the capacitance-voltage (CV) and SIMS analysis, the background [C] level was at ~ 7×1015 cm-3 (SIMS detection limit). Deep level transient spectroscopy / deep level optical spectroscopy (DLTS / DLOS) results show total electron trap concentration at ~2.5×1015 cm-3, mainly from carbon-related deep level defects. These high-quality GaN films were grown with a typical MOCVD GaN growth rate of 2 µm/hr. MOCVD GaN epitaxy with fast growth rate at 5.2 µm/hr was achieved via increasing TMGa flow rate. With a controllable Nd-Na at 1.5×1016 cm-3, the SIMS measured [C] was at 2×1016 cm-3, which is significantly increased as compared to the films grown at lower growth rates. Atomic force microscope (AFM) imaging on GaN surface shows smooth morphology with step-flow growth mode and RMS of 0.647 nm (10x10 μm scan area). The Mn incorporation from the semi-insulating ammonothermal GaN substrate into epilayer was observed from SIMS measurement. Controlled experiments show that Mn incorporation rate into epilayer is highly related to the film growth rate, sharing similar characteristics as Fe impurity. Quantitative SIMS revealed that both Mn and Fe incorporation can be suppressed with faster growth rates. Room temperature Hall measurements of GaN films show that electron mobility decreases from 852 cm2/Vs to 604 cm2/Vs (n~1.5x1016 cm-3) as the growth rate increases from 2 µm/hr to 5.2 µm/hr. In summary, systematic MOCVD GaN epitaxy and materials characterization were performed to investigate the effects of GaN growth rate on background impurities incorporation, charge compensation and charge transport properties in Si-doped GaN films. The increase of GaN growth rate leads to higher background C incorporation due to the use of higher TMGa precursor flow rate, as well as the reduction of electron mobility. This is identified as the key challenge to achieving high-quality thick GaN films with low controllable doping at low-mid 1015 cm-3. As a comparison, we will discuss the GaN film properties grown with CO2 laser excitation introduced during the MOCVD epitaxy. Acknowledgment: The authors acknowledge the funding support from Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy (DE-AR0001036), and U.S. Department of Energy&#39;s Office of Energy Efficiency and Renewable Energy (EERE) under the Advanced Manufacturing Office, FY18/FY19 Lab Call.

EMC 2021

MOCVD GaN Epitaxy with Fast Growth Rates

background carbon impurity

fast growth rate

laser-assisted mocvd

**[DOWNLOAD THE DRC 2021 DIGEST](https://drive.google.com/file/d/17_-pkYf4IBbVuNYgohTf0iZJORVGp_uN/view?usp=sharing)**

**[DOWNLOAD A COPY OF THE FINAL DRC PROGRAM](https://drive.google.com/file/d/1Ek8UIDCowpLq0z2hXav5tn67FboxS03N/view?usp=sharing)**

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Given the ongoing global health concerns associated with COVID-19 (Coronavirus), the DRC leadership has decided to hold the 2021 Device Research Conference in a virtual (online) format. This follows an enormously successful 2020 DRC held virtually, in which we had record attendance and worldwide participation of more than 875 attendees from 33 countries.

The 2021 Conference will feature:

* Informative, timely short courses in rapidly developing fields
* Oral and poster presentations on electronic/photonic device experiments and simulations
* Plenary and invited presentations given by worldwide leaders
* Evening “rump” session
* Strong student participation and Student Paper Awards

DRC is held in coordination with the Electronic Materials Conference (EMC), which will occur the same week, from June 23-25. As has happened in person in past years, in 2021, the virtual DRC and EMC sessions on the shared day, Wednesday, June 23, will be open to all attendees from both conferences. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchanges of information between attendees of both Conferences. For information on the 63rd Electronic Materials Conference, please visit the [EMC 2021 website.](https://www.mrs.org/63rd-emc/)

2021 DRC individual presentation videos will become available in Underline at the end of each technical session. A recording of each full live session with Q&A will be posted later during the conference. To facilitate re-viewing of recorded talks and sessions, the DRC Underline site will remain open through 11:59pm (US EDT) on July 7th. DRC Conference registration will remain open at www.mrs.org/drc-2021/registration through June 30th.

Thank you for joining us at the 2021 Device Research Conference!

**General Chair**
 Zhihong Chen, Purdue University

**Technical Program Chair**
 Becky (R.L.) Peterson, University of Michigan

**Technical Program Vice-Chair**
 Gregg Jessen, BAE Systems

You can register for the 79th Device Research Conference with the following link. https://www.mrs.org/drc-2021

DRC 2021

For almost eight decades, the Device Research Conference (DRC) has brought together leading scientists, researchers and students to share their latest discoveries in device science, technology and modeling. Notably, many of the first public disclosures of key device technologies were made at the DRC. This year marks the 79th anniversary of the DRC—the longest running device research meeting in the world. As we commemorate this meeting, the high-caliber technical sessions will be highlighted by plenary talks and invited talks by international research pioneers and leaders behind modern electronic technology.

Abstract Body: Gallium nitride (GaN) has been considered as a promising candidate for power electronic devices due to its wide bandgap (3.4 eV), high critical electric field (3 MV/cm), and high electron mobility (>1000 cm2/V s). As a key parameter to evaluate the performance of power devices, Baliga’s figure of merit (BFOM) of GaN is more than 500X higher than silicon (Si) and 3X higher than silicon carbide (SiC) [1]. Vertical GaN PN diode with 5kV breakdown voltage (VBR) has been demonstrated [2]. Although tremendous progress has been made in the past few years, achieving vertical GaN power devices with VBR of 10-20 kV remains challenging. Epitaxy of high-quality GaN films with a thick drift layer, low controllable doping, and high mobility is required to advance the field. In this work, the effects of increasing GaN growth rate on the impurity incorporation, charge compensation, surface morphology, and transport properties are systematically studied. Under optimized MOCVD GaN growth condition, high-quality GaN films with controllable low net charge concentration (Nd-Na) at 4×1015 cm-3 was demonstrated. Secondary ion mass spectroscopy (SIMS) measured [Si] and Nd-Na as a function of SiH4 flow rate was investigated. The compensation level at (4.8±1.0)×1015 cm-3 was extracted from the intercept of Nd-Na vs. SiH4 flow rate. Based on the capacitance-voltage (CV) and SIMS analysis, the background [C] level was at ~ 7×1015 cm-3 (SIMS detection limit). Deep level transient spectroscopy / deep level optical spectroscopy (DLTS / DLOS) results show total electron trap concentration at ~2.5×1015 cm-3, mainly from carbon-related deep level defects. These high-quality GaN films were grown with a typical MOCVD GaN growth rate of 2 µm/hr. MOCVD GaN epitaxy with fast growth rate at 5.2 µm/hr was achieved via increasing TMGa flow rate. With a controllable Nd-Na at 1.5×1016 cm-3, the SIMS measured [C] was at 2×1016 cm-3, which is significantly increased as compared to the films grown at lower growth rates. Atomic force microscope (AFM) imaging on GaN surface shows smooth morphology with step-flow growth mode and RMS of 0.647 nm (10x10 μm scan area). The Mn incorporation from the semi-insulating ammonothermal GaN substrate into epilayer was observed from SIMS measurement. Controlled experiments show that Mn incorporation rate into epilayer is highly related to the film growth rate, sharing similar characteristics as Fe impurity. Quantitative SIMS revealed that both Mn and Fe incorporation can be suppressed with faster growth rates. Room temperature Hall measurements of GaN films show that electron mobility decreases from 852 cm2/Vs to 604 cm2/Vs (n~1.5x1016 cm-3) as the growth rate increases from 2 µm/hr to 5.2 µm/hr. In summary, systematic MOCVD GaN epitaxy and materials characterization were performed to investigate the effects of GaN growth rate on background impurities incorporation, charge compensation and charge transport properties in Si-doped GaN films. The increase of GaN growth rate leads to higher background C incorporation due to the use of higher TMGa precursor flow rate, as well as the reduction of electron mobility. This is identified as the key challenge to achieving high-quality thick GaN films with low controllable doping at low-mid 1015 cm-3. As a comparison, we will discuss the GaN film properties grown with CO2 laser excitation introduced during the MOCVD epitaxy. Acknowledgment: The authors acknowledge the funding support from Advanced Research Projects Agency-Energy (ARPA-E), U.S. Department of Energy (DE-AR0001036), and U.S. Department of Energy's Office of Energy Efficiency and Renewable Energy (EERE) under the Advanced Manufacturing Office, FY18/FY19 Lab Call.

technical paper

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC), which will be held during the same week, from June 20-23. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

![](https://assets.underline.io/uploads/markdown_image/1/image/eb26c24a18d5d1030616afa4f993cf89.png)
	
<a href="https://www.mrs.org/docs/default-source/meetings-events/mrs-conference-services/2021/emc-2021/2021-emc-program-at-a-glance-6-16-21.pdf?sfvrsn=e39f950c_4">Latest Program-at-a-Glance</a>

<a href="https://drive.google.com/file/d/1eiS1ao4p83VNy8xgHs3Rls7gTQjx7Rc4/view?usp=sharing">Full Program with Abstracts</a>

Abstract Body: Core-shell semiconductor nanowires (NWs) are an attractive alternative to planar devices for multiple applications, including field-effect transistors, photovoltaic devices, light-emitting diodes, and lasers. The core-shell radial junction structure enables electron- or photo-induced electron-hole pairs (EHPs) to be collected with shorter diffusion lengths due to the small NW diameter. Furthermore, the collection of the EHPs inside the core is free from surface recombination, potentially improving the energy harvesting efficiency. Electron-induced-beam current (EBIC) measurement is a complementary technique in situ in a scanning electron microscope (SEM), collecting excess carriers in a biased diode as a function of beam position and accelerating voltage. In this talk, we will present the analysis of carrier diffusion properties in unprocessed, free standing core-shell GaAs NW diodes. The carrier kinetics in both the n-type core and the p-type shell were determined by analyzing radial EBIC profiles as a function of beam energy. These profiles are highly sensitive to changes in depletion widths and minority carrier diffusion lengths due to geometric effects. Combined with Monte Carlo simulations, they permitted measurement of the n-type core, minority carrier diffusion length, as well as the depletion widths as a function of radial direction. A relatively short minority carrier diffusion length (50 nm) found near {112}B surface facets can be attributed to bulk point defects originating from low-temperature growth (400 °C). Depletion widths were found to be smaller in <112>B directions than in <112>A, likely due to different dopant corporation efficiencies of Te and Zn in the core and the shell, respectively, and to the very thin shell on the {112}B surfaces.

Measurement of Minority Carrier Diffusion Lengths in Core-Shell GaAs NW p-n Junctions

Abstract Body: Printed electronics is an inexpensive way of producing electronic devices for every-day applications such as flexible biosensors, affordable RFID price tags and large-area optoelectronics. Transistors are the most fundamental components of many digital and analog circuits. Printed organic thin-film transistors (OTFT) consist of different functional layers deposited from solution. The conductive electrodes are commonly printed using metal nanoparticles that need to be sintered to become conductive. These electrodes are usually printed on other previously solution-processed layers. However, annealing the electrodes will impose another annealing step on the previously deposited layers. Depending on the chemical structure of these layers, their surface or bulk might undergo changes that might affect the final device performance. In bottom-contact bottom-gate organic transistors, the source and drain electrodes are printed onto the gate dielectric layer, which will undergo the electrode post-annealing. In this work, the effect of changing the annealing temperature of silver electrodes in p-type organic transistors is studied. ITO-coated glass is used as the substrate, where the ITO layer works as the gate electrode. A dielectric layer of Teflon AF 1600 (3% in Fluorinert FC-40) then covers the ITO layer through two spin-coating steps. This dielectric layer is subsequently annealed at 150°C for 30 minutes resulting in 450 nm thickness. Since this dielectric layer has low surface energy, it is not possible to form a line of connected ink droplets through printing, therefore the dielectric layer is plasma treated to increase its surface energy. Afterward, for the source and drain electrodes, silver nanoparticle ink is inkjet-printed with a custom-made printer and a 60 μm diameter nozzle. The transistors have varying channel length (20 - 75 μm) and 1.3 mm width. These electrodes are then sintered at different temperatures for 30 minutes (after 5 minutes heating at 60°C to prevent coffee ring effect). This step also acts as a second post-annealing step for the dielectric layer. Finally, the organic semiconductor PDBPyBT is spin-coated in the last step, followed by annealing at 120°C for 10 minutes. The transistors are p-type and are biased at a drain voltage of -120 V in saturation. Silver annealing temperatures of 80°C, 100°C, 120°C, and 200°C are studied. Devices annealed at 120°C show the best performance with the maximum saturation field-effect mobility of 0.13 cm2/V.s and the maximum saturation Ion/off ratio of 3.41x107. The difference in performance between different electrode sintering temperatures cannot be explained by changes in electrode conductivity because it is much lower than the channel resistance in all studied cases for this ink. The bulk dielectric properties of the Teflon gate dielectric also remain unchanged during the electrode annealing step with a dielectric constant of 2.1. However, the Teflon surface properties are changed. Water contact angle increases monotonically from 85° with no post-annealing to 120° with 200°C post-annealing. With 200°C electrode annealing, this leads to partial dewetting and accumulation of the semiconductor between the more wettable source and drain electrodes. The resulting large thickness of the semiconductor mainly deteriorates device off-state performance reducing the average on-off-ratio from 1.14x107 to 7.25x105. For 80°C, 100°C, and 120°C electrode annealing, the semiconductor thickness remains constant at 100 nm, however, the Teflon surface becomes more hydrophobic. It has been observed before that organic semiconductors perform better on more hydrophobic surfaces, which usually requires a chemical surface modification step. Here, we show that this can be achieved by a simple post-annealing step, which is already part of device fabrication to sinter the source and drain electrodes and should therefore be considered when designing the process flow of the complete device.

Effect of Annealing Printed Electrodes on Gate Dielectric Hydrophobicity and Device Performance in Organic Transistors

Abstract Body: Conjugated polymers (CPs) have found great success as active materials in organic electrochemical transistors (OECTs), which can be integrated into bioelectronic devices for cell monitoring and stimulation.1,2 The success of CPs in this application is dependent on their material design: CPs must exhibit electrochemical activity in aqueous environments and support OECT operation in the energy-efficient, accumulation mode. Current materials such as PEDOT:PSS present several challenges, including depletion mode operation in OECTs, which is less energy-efficient; water solubility, which necessitates crosslinking or post-treatment;3 and high acidity, which can limit their biocompatibility with specific cell lines.4 Consequently, there is a clear need to develop new CPs for aqueous OECTs which overcome these limitations. To this end, we have synthesised and characterised a new CP, poly(ethylenedioxythiophene) functionalised with isopropyl-protected phosphonate groups (PEDOT-Phos). This material is readily processed in organic solvents, can be proton doped with non-oxidising acids, and exhibits reversible electrochemical activity in aqueous electrolytes. Most importantly, we used PEDOT-Phos as the channel material in aqueous, accumulation mode OECTs which boast low threshold voltages and high volumetric capacitances and transconductances, without requiring additives or post-treatments. Overall, PEDOT-Phos is a promising electronic material for applications in energy-efficient, organic bioelectronics. References: (1) Hopkins, J.; Travaglini, L.; Lauto, A.; Cramer, T.; Fraboni, B.; Seidel, J.; Mawad, D. Photoactive Organic Substrates for Cell Stimulation: Progress and Perspectives. Adv. Mater. Technol. 2019, 1800744, 1800744. https://doi.org/10.1002/admt.201800744. (2) Fidanovski, K.; Mawad, D. Conjugated Polymers in Bioelectronics: Addressing the Interface Challenge. Adv. Healthc. Mater. 2019, 8 (10), 1–9. https://doi.org/10.1002/adhm.201900053. (3) Stavrinidou, E.; Leleux, P.; Rajaona, H.; Khodagholy, D.; Rivnay, J.; Lindau, M.; Sanaur, S.; Malliaras, G. G. Direct Measurement of Ion Mobility in a Conducting Polymer. Adv. Mater. 2013, 25 (32), 4488–4493. https://doi.org/10.1002/adma.201301240. (4) Mantione, D.; del Agua, I.; Sanchez-Sanchez, A.; Mecerreyes, D. Poly(3,4-Ethylenedioxythiophene) (PEDOT) Derivatives: Innovative Conductive Polymers for Bioelectronics. Polymers (Basel). 2017, 9 (12), 354. https://doi.org/10.3390/polym9080354.

Synthesis and Characterisation of Phosphonated PEDOT—An Organic Material for Energy-Efficient Bioelectronics

Abstract Body: Two-dimensional (2D) semiconductors such as transition metal dichalcogenides (TMDs) have captivated the attention of the scientific community for about a decade now because they have demonstrated a multitude of desirable properties for flexible electronics and optoelectronics. However, a major materials challenge of 2D semiconductors is that they tend to form a substantial Schottky barrier (SB) with most metals used for making electrical contacts, severely limiting both the fundamental research and electronics/optoelectronics applications of 2D semiconductors. Efforts to eliminate/minimize the SB by selecting contact metals with high (low) work function for holes (electrons) have been hampered by the nearly ubiquitous presence of Fermi-level pinning. Van der Waals (vdW) contacts have recently emerged as a promising contact-engineering strategy to minimize the Fermi-level pinning effect at the metal/2D semiconductor interface. Electrical contacts formed by transferring prefabricated metal electrodes onto 2D semiconductors demonstrated SB heights (SBHs) approaching the Schottky-Mott limit, which was attributed to the minimization of structural and chemical defects at the interface by avoiding direct metal deposition on the 2D semiconductors. However, these contacts are still depletion-type with a notable positive SBH even when the work function of metal is significantly larger than the ionization energy of 2D semiconductors, indicating that Fermi-level pinning is still present. To date, accumulation-type ohmic contacts completely free of a SB have not been experimentally demonstrated in 2D semiconductor FET devices to the best of our knowledge. We report the realization of accumulation-type vdW Ohmic contacts between nearly intrinsic WSe2 and degenerately p-doped MoS2 (p+-MoS2). Dual-gated WSe2 field-effect transistors (FETs) with p+-MoS2 bottom-contacts were fabricated as a test structure to demonstrate true Ohmic contacts free of a Schottky barrier without the need of electrostatically gating the contact regions. Despite that the back-gate electric field is screened by the p+-MoS2 bottom-contacts and the nearly intrinsic nature of WSe2, these devices exhibit ohmic behavior and similarly high performance in the back-gate as well as in the top-gate configuration (with the other gate grounded), including linear output characteristics, a high on/off ratio of 108, and two-terminal extrinsic field-effect mobility exceeding 130 cm2V-1s-1 at room temperature, which approaches the intrinsic mobility of few-layer WSe2 (~ 200 cm2V-1s-1) with further reduction of the series resistance of excess p+-MoS2. The observed ohmic behavior persists to low temperatures. Theoretical modeling shows that a p+-MoS2/WSe2 junction effectively acts as an accumulation-type metal/semiconductor ohmic contact, as signified by an extremely thin depletion region of ~ 1nm in the p+-MoS2 side of the junction and that a substantial accumulation layer of free holes in the WSe2 side. The accumulation-type ohmic contacts between p+-MoS2 and WSe2 is further verified by the results of dual-gated measurements. We attribute the accumulation-type ohmic contacts to nearly ideal metal-semiconductor interface of a vdW junction consisting of 2D materials with similar crystalline and electronic structures, where the SBH is dictated by the Schottky-Mott rule. Because the work function of p+-MoS2 (acting as a 2D metal) is slightly larger than the ionization energy of WSe2 as verified by X-ray photoelectron spectroscopy (XPS), a strong hole accumulation region develops in WSe2 at the vdW interface as predicted by the Schottky-Mott rule. The 2D vdW contacts with negligible Fermi-level pinning can also be used as the baseline to study the mechanism of Fermi-level pinning at the metal/2D-semiconductor interface. *This work was partially supported by NSF (DMR-2004445; ECCS-1849578) and the Kaskas Scholarship Funds.

Accumulation-Type Ohmic Contacts Between Degenerately Doped and Nearly Intrinsic 2D Semiconductors

Abstract Body: Atomically thin (two-dimensional, 2D) semiconductors have shown great potential as the fundamental building blocks for next-generation electronics. However, all the 2D semiconductors that have been experimentally made so far have room-temperature electron mobility lower than that of bulk silicon, which is not understood. Here, by using first-principles calculations and reformulating the transport equations to isolate and quantify contributions of different mobility-determining factors, we show that the universally low mobility of 2D semiconductors originates from the high “density of scatterings,” which is intrinsic to the 2D material with a parabolic electron band. The density of scatterings characterizes the density of phonons that can interact with the electrons and can be fully determined from the electron and phonon band structures without knowledge of electron-phonon coupling strength. Our work reveals the underlying physics limiting the electron mobility of 2D semiconductors and offers a descriptor to quickly assess the mobility. Ref: Long Cheng, Chenmu Zhang, and Yuanyue Liu, Phys. Rev. Lett. 125, 177701 (2020)

Why Two-Dimensional Semiconductors Generally Have Low Electron Mobility

Abstract Body: Transition metal dichalcogenides (TMDCs) are considered promising channel materials in future sub-5nm transistors due to their atomic-scale thickness, dangling bond-free surface and excellent electrical properties. However, the large contact resistance at the source/drain interface is still a critical issue that limits 2D TMDCs device performance. The contact resistance is affected by the Schottky barrier height (SBH) between the TMDC and the metal contact. Various contact engineering approaches have been explored to lower the SBH, such as optimizing the contact metals, chemical doping, plasma treatments, phase engineering, and others. One of the advantages of TMDCs in this regard is that many can exist in either a metallic or semiconducting phase, which, a property that can be used to. In our previous work, a lateral homojunction of semiconducting 2H-MoTe2 and metallic 1T’-MoTe2 was synthesized in-situ. FETs made on these homojunctions demonstrate an improvement of device performance due to substantially decreasing of the contact resistance compared to direct metal/2H contacts. Those results showed that the SBH of the 1T’/2H contact was much lower than the metal/2H interface. However, in-situ grown homojunctions lack controllability and scalability which limits its applications in TMDCs based devices. Here, we characterize sequential CVD techniques that can be generalized to any combination of TMDC materials. To date, we characterized sequentially-grown 1T’/2H homojunctions where the 1T’ material is MoTe2 and the 2H material is MoTe2, MoS2 and WS2. In all of these structures, the 2H material was first synthesized by CVD on a SiO2/Si substrate, then metallic 1T’-MoTe2 was synthesized by flux-controlled tellurization of molybdenum thin film. The technique shows capability of integration different TMDCs into heterostructures with controllability and compatibility with CMOS fabrication technique which is critical for both technological applications and fundamental sciences. The technique can both be applied to vertical or lateral heterostructures as well. In this paper, we will describe Raman spectra that show two distinct regions of TMDCs which indicates a successful integration of the differing TMDCs materials. We also describe FET made on the sequential-grown MoTe2 homojunctions, which show comparable electrical performance with the previously reported in-situ-grown MoTe2 homojunctions. 2H-MoS2/1T’-MoTe2 and 2H-WS2/1T’-MoTe2 heterostructures also show operational devices which indicates the potential to extend the technique to other TMDCs materials.

Transition Metal Dichalcogenides (TMDCs) Heterostructures Field Effect Transistors (FETs) Fabricated by Sequential Chemical Vapor Deposition (CVD)

Abstract Body: Doping is fundamental to CMOS technology. While large-scale synthesis of two-dimensional transition metal dichalcogenides (2D TMDCs) is maturing, controllable and scalable doping in 2D TMDCs must be established before integration in next-generation electronic, logic-memory, and magnetic devices. While ion implantation works well for bulk and thin film silicon, it is difficult to achieve in 2D materials due to their ultrathin nature, therefore other doping methods should be explored to satisfy this technological need. Substitutional doping is a promising candidate for scalable, tunable doping of 2D TMDCs. In this work we use metal organic chemical vapor deposition (MOCVD) to synthesize high quality Re-doped MoS2. Employing Re2(CO)10 as a gas-source dopant precursor within the MOCVD process, we exhibit unprecedented control over Mo-substitutional doping concentration confirmed by a combination of X-ray photoelectron spectroscopy and Time-of-Flight Secondary Ion Mass Spectrometry measurements. By being able to precisely control precursor injection, we elucidate the importance of dopant introduction timing on doping efficiency. We find that when the dopant is introduced during the nucleation stage, Re incorporated into the lattice is enhanced by ~30% compared to when the dopant is introduced exclusively in the lateral growth stage. Having optimized the substitutional doping process, we show that the dopant ionization energy is large in the monolayer limit due to both quantum confinement effects and reduced dielectric screening. The high ionization energy of Re in ML Re-MoS2 prevents dopant activation and results in deteriorating transport properties with higher doping levels. Finally, we will discuss the impact of layer number on dopant ionization energy and carrier concentration based on scanning tunneling microscopy and spectroscopy and field-effect-transistors transfer characteristics.

Controlled Rhenium Doping of MoS2

Abstract Body: 2D transition metal dichalcogenides (TMDs) have become a topic of intense interest due to their fascinating electronic properties at atomic thicknesses. In particular, molybdenum disulfide (MoS2) sparks interest due to its useful semiconducting behavior for devices such as field effect transistors (FETs). As novel materials are introduced as candidates for 2D FETs, parameters such as the contact resistance must be reduced to develop devices that do not suffer from significant parasitic losses. Hybrid top/edge metal contacts, such that the metal contacts the semiconductor at both the lateral and longitudinal interfaces, are suggested to reduce the overall contact resistance. This idea is inspired by experimental observations indicating that the contact resistivity at the edge is lower than at the top1, while top contacts contribute more effective area to aid in reducing the overall contact resistance. This investigation aims to provide a computational model that studies the changes in overall specific contact resistance when hybrid top/edge Au contacts are prepared on MoS2, similar to a prototype lateral contact recently demonstrated in our lab for field effect transistors2. COMSOL Multiphysics is used to create a resistor circuit model of the Au/MoS2 contact. Au rectangular prisms are used to model embedded Au nano-islands, with identical edge contact resistivities applied to each surface of the prism. Control cases that examine the potential drop for a system with only a top contact or edge contact are constructed, and the numerical solution is compared to known solutions. Solutions for the potential drop and current densities across the hybrid contact are then analyzed and compared to control cases. For a fixed top contact resistivity of 10 kΩ*μm2, for example, edge contact resistivities between 0.01 kΩ*μm2 – 10 kΩ*μm2 were examined. Hybrid contacts with edge contact resistivities between 0.01 kΩ*μm2 – 1 kΩ*μm2 resulted in a lower overall contact resistance. Systems with smaller yet more plentiful islands also result in a lower overall contact resistance compared to systems with larger islands; however, cases where the edge contact resistivity were >1 kΩ*μm2 led to an increase in contact resistance. These specific trends hold for sheet resistances from 2.5 kΩ – 250 kΩ. This model will aid in the design of hybrid contacts to MoS2 and other very thin layered semiconductors. References 1M. H. D. Guimarães et al., “Atomically Thin Ohmic Edge Contacts between Two-Dimensional Materials,” ACS Nano, 2016, doi: 10.1021/acsnano.6b02879. 2T. N. Walter, N. Oliver, and S. E. Mohney, “Electron beam evaporated Au islands as a nanoscale etch mask on few-layer MoS2 and fabrication of top-edge hybrid contacts for field-effect transistors,” Nanotechnology, 2021, doi: 10.1088/1361-6528/abbb4a.

Computational Modeling of Metal Islands for Hybrid Contacts to MoS2

Abstract Body: Abstract: Ultrawide Bandgap AlxGa1-xN channel metal oxide semiconductor heterostructure field effect transistors (MOSHFETs) are promising candidates for high-power, high-temperature harsh environment applications. In our recent reports on Al0.4Ga0.6N-channel MOSHFETs with high-k ZrO2 and Al2O3 gate-dielectrics we found that, these dielectrics introduce negative fixed charges (Qox) as high as 1-3×1013 cm-2 depleting 2DEG density of 2×1013 cm-2 causing a positive shift of threshold voltage (VTH) compared to that for HFET (no gate dielectric). This is an important step toward realizing enhanced (E-) mode MOSHFET. Our data show that, ZrO2 possesses higher Qox resulting in stronger positive VTH shift in devices, while devices with Al2O3 demonstrate lower gate leakage. In this work we use stack of ZrO2/Al2O3 to fabricate MOSHFETs. E-mode device was realized using ZrO2/Al2O3 combined with gate recess. To separate effects of dielectric charges and damage from recess process on device performance depletion (D-) mode and E-mode devices were fabricated on the same wafer. Temperature dependent VTH instability of these MOSHFETs were studied and potential mechanism for this VTH instability is discussed. Experimental: The pseudomorphic device structure was grown using metalorganic chemical vapor deposition on a AlN/sapphire template. A graded composition (AlxGa1-xN, x=1-0.4) back barrier was grown to reduce internal stress and improve gate control in the devices[i], [ii] while the top 20 nm graded n-AlxGa1-xN (x from 0.6 to 0.3) was grown to facilitate ohmic contacts. The contact resistance was as low as 1.7 Ω-mm and the 2DEG sheet resistance was ~1900 ohm/sq. Device processing details published elsewhere.[iii] The fixed gate-length LG ≈ 2.0 μm, source to drain spacing, LSD=6 μm, were used for regular devices with 15 μm channel width, while for precise C(V,T,f) measurements we use a test structure with gate area 200x80 μm2 . Results and discussion: The combination of gate recessing and ZrO2/Al2O3 stack resulted in VTH shift of +12.2 V from D to E-mode device. The peak DC currents for D and E-mode devices were found to be 1.1 A/mm and 0.48 A/mm respectively at gate voltage +12 V while in the pulse mode it was 1.3 A/mm and 0.53 A/mm. The gate leakage current in both D and E-mode MOSHFETs is suppressed by ~3 orders of magnitude compared to that of MOSHFETs using singe Al2O3 or ZrO2 layer. ON/OFF ratio as high as 3×108 was achieved which is higher than ~2 orders of magnitude than that for Al2O3 or ZrO2. Temperature dependent VTH and gate leakage study was performed on the fabricated MOSHFETs. It has been found that, from RT to 150 °C there is VTH shift of + 1.7 V and -2.9 V for D- and E-mode MOSHFETs respectively. The VTH shift for similar device having Schottky gate HFET was found to be significantly smaller, +0.2 V which indicates that the VTH shift in MOSHFETs is mainly due to the charges in dielectric or at dielectric-barrier interface. In the E-mode devices, the effective channel mobility (µ) and VTH was additionally affected by radiative defects introduced during gate-recess. µ in D-mode devices decreases with temperature while it increases for the E-mode devices. Temperature dependent interface state density (DIT(T)) and Qox (T) were estimated using frequency- dependent C-V measurements. Our analysis show that in D-mode device, Qox(T) dominates over DIT(T). These fixed negative charges (Qox) deplete the channel giving a total VTH shift of +1.7 V. The extracted SS values of 99 mV/decade (D-mode) and 134 mV/decade (E-mode) indicate an increased density of DIT at the recessed interface in E-mode device. In E-mode, the DIT value is comparable to Qox, thus compensating the temperature effect on Qox and making the VTH more negative. [i]) G. Simin et al., Jpn. J. Appl. Phys., 40, L1142 (2001). [ii]) C. Ren et al., J. Semicond. 36, 014008-1 (2015). [iii]) S. Mollah et al., Appl. Phys. Express. 14, 014003 (2021).

Study of Temperature Effect on Performance of Ultrawide Bandgap Al0.4Ga0.6N-Channel Depletion and Enhancement Mode MOSHFETs with ZrO2/Al2O3 Gate Insulator

Abstract Body: As silicon technology reaches its practical and theoretical limit, III-nitride materials offer a promising alternative to maintain the growing demand for high power electronic devices. Current GaN devices already show promising results, offering higher breakdown voltages and reduced on resistances compared to their silicon predecessors. However, these devices are still limited by the classical Baliga figure of merit (BFOM). In order to surpass the BFOM, novel device geometries have been introduced such as the superjunction (SJ). The concept of the SJ has been demonstrated in silicon, with devices such as CoolMOS which have surpassed the BFOM. To date, there are no demonstrations of III-nitride SJs in the literature. In order to achieve III-nitride SJs, there are several research barriers to address. First, the necessity for alternating, lateral n- and p-type doping regions with zero net charge. The inherent polar doping selectivity of GaN can be used to achieve the doping scheme for a lateral GaN p/n junction. Oxygen, which unintentionally incorporates into N-polar GaN at levels >1019 cm-3, acts as the n-type dopant, whereas Ga-polar GaN does not readily incorporate oxygen. Accordingly, lateral polarity junctions (LPJs) with alternating domains of O doped N-polar and Mg doped Ga-polar GaN have been fabricated to realize lateral p/n junctions. Second, the proper doping profiles must be attained in the N- and Ga-polar domains for SJ operation. For drift regions, the n-type doping in the N-polar domain (and p-type doping in Ga-polar domain) must be reduced to ~1017 cm-3 for micron wide domains. By implementing the chemical potential control (CPC) framework, MOCVD process conditions were designed in order to decrease the oxygen concentration by increasing the growth supersaturation. This led to a reduction in oxygen from >1019 cm-3 to low 1017 cm-3. Third, due to the difficulty of making reliable Schottky contacts to the N-polar surface, the alternating Schottky/ohmic contacts on a typical superjunction are replaced with alternating p+/n- junction (N-polar) and p+/p- junctions (Ga-polar). In this direction, a N-polar p/n junction with rectifying behavior comparable to a Ga-polar p/n junction was achieved. Finally, the growth of a GaN LPJs must exhibit N-/Ga-polar domains with a smooth surface and equal growth rates. It is understood that supersaturation can be used to control the surface morphology, relative growth rates, and defect incorporation of the domains. However, the high supersaturation required to realize the necessary doping profile for SJ operation contradicts the intermediate supersaturation conditions required to obtain a smooth surface morphology and equal domain growth rates. It must be noted that high supersaturations result in low O N-polar dominated growth, and low supersaturations in Ga-polar dominated growth. To overcome these anticorrelated requirements, we demonstrate a supersaturation modulated growth (SMG) where the V/III ratio, and thus supersaturation, was modulated between low and high values. A GaN LPJ with a smooth surface and equal domain heights, with the necessary doping profile is hence demonstrated.

MOCVD GaN Epitaxy with Fast Growth Rates

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MOCVD GaN Epitaxy with Fast Growth Rates

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