United States

Abstract Body: Vanadium dioxide (VO2) is well-known for its temperature-driven metal-to-insulator transition between the monoclinic (M1) phase and the rutile (R) phase, which is accompanied with abrupt changes in electrical and optical properties. These intriguing changes have attracted great interest and promises a lot of potential applications. However, the phase transition of bulk VO2 usually occurs around 68 °C with significant thermal hysteresis induced by the latent heat of the first-order transition. The relatively high phase transition temperature Tc and broad hysteresis width ΔTc are adverse to its practical application. Therefore, the modulation of its phase transition behavior is quite necessary. Accumulating evidence suggests that the strain state plays an important role in the phase transition behavior of VO2 and it has been confirmed that the specific strain between VO2 and TiO2 can significantly reduce Tc[1, 2]. Based on this, in order to finely modulate the phase transition behavior and further investigate its relationship with strain state, we inserted TiO2 epitaxial film between VO2 film and the (100) α-Al2O3 substrate as the buffer layer. By controlling the thickness of both VO2 film and TiO2 buffer layer, the variational strain state can be introduced and further lead to the change of lattice parameters and phase transition behavior of VO2 film. Specifically speaking, when both VO2 and TiO2 layers are thin (~10 nm), these two layers are highly strained to the Al2O3 substrate. Due to inconsistent lattice mismatch between [100] and [010] direction, the lattice parameter a and b of VO2 will be stretched and compressed respectively, leading to the suppression of phase transition. If increasing the thickness of TiO2 layer to 200 nm and maintaining the VO2 thickness of 10 nm, due to the lattice relaxation, TiO2 will be relaxed to the rutile phase. As the result, the structure of VO2 layer which is still strained to TiO2 will change synchronously and exhibit the sharper phase transition with reduced Tc of ~34 °C. This phenomenon is similar to the VO2 film epitaxially grown on TiO2 substrate. Lastly, by further increasing the VO2 thickness from 5.5 to 50 nm, the VO2 layer will also tend to be relaxed to bulk M1 phase and the Tc can be continuously adjusted in a wide range from 34 to 58 °C. More interestingly, when the VO2 is thicker than 30 nm, the ΔTc is extremely narrowed to ~0.4 °C and the lattice parameter c exceeds the bulk value correspondingly. We consider the strain-induced lattice parameter change can modify both of the Tc and ΔTc. And by controlling the strain state, the phase transition behavior of VO2 can be finely designed. These results may be useful for the design of VO2-based functional material and device. [1] Y. Muraoka, Z. Hiroi, Appl. Phys. Lett. 80, 583-585 (2002) [2] N. B. Aetukuri et al., Nat. Phys. 9.10, 661-666 (2013)

EMC 2021

Reduction of the Tc and Suppression of the △Tc of VO2 Epitaxial Films on TiO2 Buffered Sapphire Substrate

film

metal-to-insulator transition

pulsed laser deposition


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The energy cost of storing and moving data is enormous, and is growing at such a rapid pace that within a few years the power demand may overwhelm some developed nations. Non-volatile memory (NVM) and neuromorphic computing are enabling critical advances in this area, but there are many scientific and technological challenges. This conference will cover the materials challenges of different memory technologies, from the fundamental processes and mechanisms, to industry perspectives on materials specifications and manufacturing.

Materials Challenges for Memory

technical paper

The Electronic Materials Conference (EMC) is the premier annual forum on the preparation, characterization and use of electronic materials. This year’s event will feature a plenary session, topical sessions, a poster session and more.

EMC is coordinated with the Device Research Conference (DRC), which will be held during the same week, from June 20-23. This recognizes the strong interaction between device and electronic materials research and provides fruitful exchange of information between attendees of both Conferences.

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<a href="https://drive.google.com/file/d/1eiS1ao4p83VNy8xgHs3Rls7gTQjx7Rc4/view?usp=sharing">Full Program with Abstracts</a>

Abstract Body: A two-dimensional, solid-state, non-volatile memory has been demonstrated using electric double layer (EDL) gating of two-dimensional (2D) field effect transistors (FETs) with nanosecond scale switching speeds. In EDL gating, oppositely charged ions are accumulated near the 2D semiconductor surface, which induce image charges in the channel. This approach yields large capacitance densities corresponding to sheet carrier densities on the order of 1013 -1014 cm-2. The monolayer electrolyte random access memory (i.e., MERAM) consists of cobalt crown ether phthalocyanine (CoCrPc) and lithium ions deposited as a monolayer on the surface a 2D semiconductor (WSe2) by drop casting and annealing. CoCrPc is an electrically insulating (band gap ~ 1.34 eV) material with four crown ethers and it lays flat on the surface of a 2D semiconductor. Each crown solvates a Li+ ion that can diffuse up or down through the crown ether cavity. In response to an applied electric field, Li+ ions diffuse through the crown ether cavity and are positioned either near or away from the channel resulting in on and off states, respectively. We have previously shown switching behavior on 2D FETs using this material with potential application in non-volatile memory. Achieving well-ordered monolayers of CoCrPc and complete solvation of Li+ into the crown ethers are critical for device operation because the location and orientation of the molecules governs the device mechanism. When the well-ordered electrolyte layer deposited on a WSe2 FET is capped with h-BN, the off-state is stabilized (as confirmed by density functional theory (DFT)) by providing an energetically favorable state to Li+ ions. We have demonstrated the bistability using back-gated pulsed voltage testing with pulse width of 1 sec (± 30 V). Switching speeds down to 50 nanoseconds (limit of the instrument) are demonstrated with an on-off current ratio > 103. Further, we performed the endurance test on the device and demonstrated the stability of the device for 1000 cycles (max. measured) with 50 ns pulse. The on-off current ratio was maintained (> 103) even after 1000 switching cycles. Current work includes quantifying performance metrics for several devices and top-gating these devices to decrease program/erase voltages.

High-Speed Two-Dimensional Solid-State Non-Volatile Memory Based on Electric Double Layer Gating Using a Monolayer Electrolyte

Abstract Body: Nanowire light-emitting diodes (LEDs) have long been investigated as alternatives to conventional mesa LEDs, as they allow for increased light extraction efficiency (LEE) and a reduction of the internal electric field strength in AlInGaN alloys. Nanowires also show potential for use as single pixels in micro-LED (µLED) displays and photonic crystal surface-emitting laser diodes (PCSELs). While epitaxially grown nanowires allow for higher material quality in the active region and reduction of the quantum confined Stark effect, they often suffer from uniformity and yield issues, and are difficult to fabricate into ordered, addressable arrays. Nanowires can alternatively be formed through dry-etching of epitaxially grown light emitting layers, taking advantage of processes and tools developed by the semiconductor industry. The general process for fabricating a nanowire array LED involves dry-etching of an n-i-p epitaxial stack to form high aspect ratio structures, followed by deposition of the n-contact metal, application of an interlayer dielectric, and deposition of the p-contact material. As most LEDs emitting in the visible range are based on the AlInGaN material system, an aggressive Cl2 plasma must be used to perform the dry-etch. The poor selectivity of Cl2 plasmas against conventional dry-etch hardmask materials such as photoresist and SiO2 necessitates the use of a metal hardmask such as Ni, which is capable of withstanding the extended etch times required to form nanowires with heights greater than 1 µm. This thick Ni hardmask must be removed from the nanowires in order to maximize LEE. In devices which use self-masked n-metal deposition, in which the nanowires themselves act at the mask for deposition of a universal n-contact, wet etching of the Ni hardmask following deposition of the n-metal (which itself often contains Ni) is not possible, because the chemistries commonly used to etch Ni will also attack the other metals in the n-metal stack (Ti, Al, Ni, etc.). For this reason, an alternative method of removing the Ni hardmask is desired. In this work, we present a novel method for removing a metal hardmask from the tops of dry-etched GaN nanowires which does not involve metal etch chemistry, but instead relies upon an underlying “liftoff” layer to separate a thick metal “cap” from the tops of the nanowires. A 300 nm layer of SiO2 is deposited on the wafer, followed by patterning of the Ni hardmask through a liftoff process. The Ni is then used to mask a CF4/CHF3 dry-etch of the underlying SiO2, and a subsequent Cl2/Ar dry-etch of the GaN, with ~200 nm of Ni capable of withstanding etch depths of more than 7 µm. The nanowires are then etched in a KOH solution to remove dry-etch damage and smooth the sidewalls of the nanowires. A universal n-metal (Ti/Al/Ni/Ag) contact, masked by the nanowires themselves, is then deposited and annealed. A buffered oxide etch (BOE) solution is then used to remove the SiO2 layer, releasing the thick metal caps (Ni/Ti/Al/Ni/Ag) which are washed away in the etch solution. Polydimethylsiloxane (PDMS) is then coated over the “bare” nanowires and etch-back to expose the p-GaN nanowire tips. A transparent top contact, either ITO or thin (<20 nm) Ni is then deposited, making contact to the tops of the nanowires and linking many of them in series, allowing for electrical excitation of arbitrarily large arrays simultaneously. Using this process, we have fabricated high brightness arrays of 2.5 µm diameter electrically driven nanowires emitting at 550 nm with a linewidth of ~40 nm. Removal of the metal cap from the nanowires allows for increased LEE from extremely uniform arrays, while the use of a universal n-metal contact allows for decreased series resistance and more uniform emission intensity from larger arrays. This novel fabrication approach can allow for more efficient top-down fabricated light-emitting nanowire arrays, which are of interest for use in LEDs, µLED displays, and PCSELs.

Realization of High-Efficiency Green InGaN Nanowire Light-Emitting Diodes Using a Novel Dry-Etch Hardmask Removal Process

Abstract Body: Organic photovoltaics (OPVs) based on nonfullerene small molecule acceptors have been the subject of renewable energy research in the past five years. Ternary photovoltaic blends comprising a polymer donor, a nonfullerene small molecule acceptor, and a fullerene acceptor have proved to be most efficient active layers for OPV devices. However, the morphological parameters and their relations with mechanical properties and photovoltaic performance of this type of highly efficient polymer:nonfullerene:fullerene OPVs are still unknown to date. To address this question, we characterized the thin-film microstructure and mechanical behavior of the best-performing ternary OPV active layer (PM6:N3:PC71BM). Specifically, we alter the relative weight ratio of acceptors and systematically examined the composition dependence of photovoltaic performance, surface/bulk morphology, and mechanical parameters of the ternary blend films. It is shown that the addition of 20 wt% PC71BM to the acceptor component results in the highest power conversion efficiency (PCE) and crack-onset strain (COS) (Figure 1a). Most notably, we discover that it is possible to predict the elastic modulus of the ternary blend films by an extended Halpin-Tsai model (Figure 1b). This work provides simple guidelines for predicting the mechanical properties of many electronic devices based on ternary blends.

Manipulation of Morphological, Mechanical and Photovoltaic Properties of Ternary Organic Photovoltaic Blends for Optimum Operation

Abstract Body: Metal halide perovskites (MHPs) have rapidly become a topic of intense interest in both materials physics and device engineering due to their much sought for properties like high charge carrier mobilities, tunable bandgap, and low-cost processability. Various high-performance devices based on MHPs, including photovoltaic cells, light-emitting diodes, transistors and photodetectors have been reported, but a thorough understanding of the mechanism of charge transport and photo-transport in this material is still lacking. Here, we explore the photocurrent properties in bilayers consisting of small molecule organic semiconductors (OSCs) and MHPs. The MHP CH3NH3PbI3-xClx was the primary photoactive layer and electron transport layer, while the OSC hole transport layer was 2,8-Difluoro-6,13-Bis(triisopropylsilylethynyl) anthradithiophene (diF-TIPS-ADT). We found that the responsivity of the bilayer optimized device was 28 times greater than neat perovskite film, reaching values as high as 6.4 A/W. Detectivity also improved by a factor of 9, to 1.4*1011 Jones, in devices with optimum film morphology. We found that the photoresponse can be tuned by altering the microstructure of the organic semiconductor: treatment of the device contacts with (2,3,4,5,6)-Pentafluorothiophenol (PFBT) resulted in grains as large as 155 µm2 (LG) within the OSC, compared to much smaller grains (SG) seen when the OSC was deposited on the bare Au contacts, which resulted in grains in the order of 10 - 15 µm2. Additionally, in the heterostructure devices made on a large grain OSC film, hysteresis was eliminated. X-ray diffraction measurements indicate that the crystal structure of both the OSC and MHP is similar in all samples, with diF-TIPS-ADT preferentially oriented with its (001) plane parallel to the substrate, and MHP adopting its tetragonal phase. We concluded that the observed performance improvement does not originate from differences in the interfacial coupling related to molecular orientation or differences in MHP crystal phase. Instead, we conclude that reducing charge trapping at grain boundaries within the OSC layer extends photocarrier lifetime, leading to an improvement in performance.

Photocurrent Enhancement in Organic Semiconductor/Metal Halide Perovskite Bilayers

Abstract Body: Resistive switching memory devices are being widely studied due to their excellent characteristics such as high scalability, non-volatility, and fast operation speed. Organo-metal halide perovskite (OHP), which is solution-processable and has outstanding optical and electrical properties, is also applied to a resistive memory device. OHP resistive memory has the advantage of being able to operate with a low voltage and large ON/OFF ratio [1]. On the other hand, random distribution in operation voltage remains a challenge in memory application. This stochastic operation characteristic is due to the random formation of conducting filaments that cause resistance changes in the material. Therefore, studies on the structure of the conducting filament are important. However, observing a nano-scale structure is difficult. Moreover, there is insufficient research on how the conducting filaments are formed in OHP materials. In this presentation, the geometric shape of the conducting filaments formed in the perovskite was explored through a current noise analysis. By observing the electrical properties and current noise under different temperature conditions, we investigated how the temperature condition affects the formation of the conductive filaments [2]. Through this, more advanced understanding of the operating mechanism of the perovskite resistive memory device will be possible. References [1] K. Kang, H. Ahn et al., Adv. Mater. 31, 1804841 (2019). [2] H. Ahn et al., manuscript in preparation.

Current Noise Analysis on Organo-Metal Halide Perovskite Resistive Switching Memory

Abstract Body: Diverse types of molecules such as a donor-s-acceptor molecules and ferrocenyl alkanethiol have been suggested as potential candidates for the electronic component of a molecular rectifier.[1,2] Recently, we demonstrated a novel strategy and design rule for realizing molecular-scale diode features based on the energy band engineering between simple alkanethiol or conjugated molecules and two-dimensional (2D) semiconductors.[3] Here, we firstly suggest a molecular-scale (sub-2nm) selector where is based on a heterojunction structure with a non-functional molecule(1-octanethiol, tridecafluoro-1-octanethiol) and two-dimensional semiconductor(MoS2, WSe2), which can be utilized to prevent the crosstalk signal in the crossbar memory array. According to direction of molecular dipole moment, the type of 2D semiconductors (1L-MoS2 of n-type), and the metal work function (Au and Pt), we found the nonlinearity at Vr/2 scheme can be significantly varied, e.x., 1.2± 101 for Au/C8/1L-MoS2/Au and 3.5 ± 102 for Au/F6H2/1L-MoS2/Pt. This phenomenon can be understood based on the interfacial energy band adjustment of 2D semiconductor in molecular heterojunction according to the direction of molecular dipole moment. The maximum non-linearity value is found to be 2.7± 103 for the case of Au/F6H2/1L-MoS2/Pt. With this non-linearity, the suggested molecular selector enables to extend the array size up to ~ 9Gbit crossbar array. [1] Díez-Pérez, I. et al. Rectification and stability of a single molecular diode with controlled orientation. Nat. Chem. 1, 635 (2009). [2] Chen, X. et al. Molecular diodes with rectification ratios exceeding 105 driven by electrostatic interactions. Nat. Nanotechnol. 12, 797 (2017). [3] Shin, J. et al. Tunable rectification in a molecular heterojunction with two-dimensional semiconductors. Nat. Commun. 11, 1412 (2020).

Molecular-Scale Selector Implemented by a Combination of Different Molecular Dipole Orientation and Two-Dimensional Semiconductors

Abstract Body: A wearable neuromorphic electronic system, that can learn and interpret the non-structural biometric information at extremely low-power, has been brought great attention because of its applicability as the intelligent device that can easily attach onto the human body or any rough surface [1-3]. With this reason, organic-based artificial synaptic devices have been proposed as a potential candidate for wearable neuromorphic applications due to its inherent mechanical flexibility and the material (or device form) variability for the desired functionalities [2,3]. In this study, we designed 1D fiber-shaped multi-synapses comprising ferroelectric organic transistors fabricated on a 100 mm Ag wire and utilized them as multi-synaptic channels in an e-textile neural network for wearable neuromorphic applications. The device mimics diverse synaptic functions, including short- and long-term plasticity with 80 states and spike rate- and timing-dependent plasticity. It exhibited excellent reliability even under 6,000 repeated input stimuli and mechanical bending stress. Various NOR-type textile arrays are formed simply by cross-pointing 1D synapses with Ag wires, where each output from individual synapse can be integrated and propagated without undesired leakage. Notably, the 1D multi-synapses achieved up to ~90% and ~70% recognition accuracy for MNIST and electrocardiogram patterns, respectively, even in a single-layer neural network, and almost maintained regardless of the bending conditions. References [1] Park, Y.; Park, M.-J.; Lee, J.-S. Adv. Funct. Mater. 2018, 1804123 [2] van de Burgt, Y.; Lubberman, E.; J. Fuller, E.; T. Keene, S.; C. Faria, G.; Agarwal, S.; J. Marinella, M.; Talin, A. A.; Salleo A. Nat. Mater. 2017, 16, 414-418 [3] Jang, S.; Jang, S.; Lee, E.-H.; Kang, M.; Wang, G.; Kim, T.-W. ACS Appl. Mater. Interfaces 2019, 11, 1071-1080 [4] *S. Ham et al. Sci. Adv. 2020, 6, eaba1178 [Published]

Fiber-Shaped Multi-Synapses Enabling an Electronic-Textile Neural Network for Wearable Neuromorphic Applications

Abstract Body: Newly emerged wide bandgap semiconductor (WBG) β-Ga2O3 has been extensively researched for power electronics, RF electronics and optoelectronics due to its large bandgap of 4.7- 4.9 eV and high breakdown field of ~ 8 MV/cm. Due to the absence of p-type Ga2O3, most of demonstrated β-Ga2O3 devices are unipolar devices such as high electron mobility transistors (HEMTs) and Schottky barrier diodes. To overcome this limitation, other p-type materials, such as GaN and NiO, have been investigated to produce Ga2O3 based p-n heterojunctions. Among these p-type materials, p-GaN has attracted especial interests since GaN is also a WBG semiconductor and has a clear crystallographic relationship to β-Ga2O3 for epitaxial growth. In addition, both β-Ga2O3 and GaN can be produced in the industrial standard tools, i.e., the metalorganic chemical vapor deposition (MOCVD). The growth of high-quality GaN on Ga2O3 by MOCVD has been recently reported. β-Ga2O3/GaN p-n heterojunction via mechanically exfoliation also showed decent rectifying behaviors. However, the breakdown capability of the β-Ga2O3 based p-n heterojunctions is still far from expectations due to the lack of effective edge terminations. Here we design and simulate mesa based edge terminations for the vertical β-Ga2O3/GaN p-n heterojunctions using SILVACO TCAD simulator. The model was first calibrated by the experimental results, including the conduction and valance band offsets of the heterojunction and electrical properties. The device structure consisted of n+-Ga2O3 n-contact layer, 5 µm unintentionally doped (UID) β-Ga2O3 drift layer and 500 nm p-GaN layer. The ideal breakdown voltage (BV) of the heterojunction was 1.37 kV, while the BV of the reference device without effect mesa edge termination dropped dramatically to 300 V due to the electric field crowding at the device edge. Therefore, it is critical to design and optimize the mesa edge termination to improve the BV of the β-Ga2O3/GaN p-n heterojunctions. Three mesa edge termination structures were investigated in this work: beveled mesa, step mesa, and deeply-etched mesa. The beveled mesa angle θ is the key parameter in determining the device BV. When θ was varied from 15° to 90°, the highest BV of 1224 V was obtained for θ =15°. For the step mesa edge termination, the width (W), depth (D), and the number of steps define the mesa structure. It was found that the BV of the devices increased with increasing number of steps. The combination of (W, D) values of (0.5,0.5) and (0.5,1.0) and (1.0,1,0) was investigated, where all the values are in µm. The highest value was obtained for W = 0.5µm, D = 1.0µm and the number of steps = 5. Smaller W and larger D led to better BV. The electric field distributions of devices with different mesa edge terminations were compared at –300V. Without effect mesa edge termination, the peak electric field at the junction edge was ~ 4.2 MV/cm. By incorporating the mesa edge termination techniques, the electric field crowding at the device edge was mitigated, and the peak electric fields were reduced to 1.8 MV/cm and 2.4 MV/cm for the beveled and step mesa edge terminations, respectively. For the deeply-etched mesa structure, it was found that a more uniform electric field distribution was observed when the mesa depth was increased from 0.5,1.0, 2.0, to 3.0 µm, where the peak electric fields were decreased from 2.1, 1.8 ,1.5 to 1.2 MV/cm, respectively. In summary, this work presents a comprehensive design and optimization of mesa edge terminations for the wide bandgap vertical β-Ga2O3/GaN p-n heterojunctions, which is first of its kind. Three mesa structures were explored, including beveled mesa, step mesa and deeply-etched mesa. It was found that these mesa edge terminations can alleviate the electric field crowding at the junction edge and increase the device BV. This work can provide critical guidance for the development of high-performance β-Ga2O3 based bipolar high voltage and high power devices.

Vertical Wide Bandgap β-Ga2O3/GaN p-n Heterojunction with Mesa Based Edge Termination

Abstract Body: β-Ga2O3 is of high interest for high voltage and high-power DC and microwave applications. Point defects and extended structural defects in bulk crystal and epitaxy layer are likely responsible for poor device performance. The fundamental properties of instability under high reverse bias (device degradation mechanism) are still poorly understood. Here, changes of I-V and C-V curves of schottky diodes based on MOVPE films and UID crystals can be observed at relatively low temperature after a high current density (0.1 mA/cm2) stress. About 1.6um-thick UID Ga2O3 epitaxial film were grown by MOVPE on (010)-oriented NCT Fe-doped substrate using triethyl gallium, diluted silane and oxygen precursors. UID crystals were grown by Czochralski method. The defect properties for the pristine and stressed devices will be investigated by deep level transient spectroscopy (DLTS).

Temperature Dependent Current Stress of β-Ga2O3 Schottky Devices

Abstract Body: β-Ga2O3 has become a promising semiconductor for high power applications. High-quality dielectrics are crucial for enabling high performance β-Ga2O3 field-effect transistors (FETs) especially because achieving p-type doping does not seem feasible for this material system. The material properties of high-quality gate dielectric include high dielectric constant, negligible gate leakage, low density of interface and bulk traps, and large breakdown field. Recently, aluminum silicon oxide (AlSiO) has been proposed as a high-performance and reliable gate dielectric for GaN-based devices [1], [2]. Previous studies showed that the alloying of Al2O3 with silicon to form AlSiO has the potential to combine the merits of both SiO2 and Al2O3 thus realizing low density of interface traps (Dit), high conduction/valence band offset and high breakdown strength [3], [4]. The promising results of AlSiO as a dielectric for GaN-based devices motivated us to expand its applications to Ga2O3. In this work, the interface and bulk properties of aluminum-silicon-oxide (AlSiO) dielectric grown by metal-organic chemical vapor deposition (MOCVD) on (001) β-Ga2O3 were investigated systematically using a deep UV-assisted capacitance-voltage methodology. The AlSiO dielectric, with a silicon composition of 40%, was grown by metal organic chemical vapor deposition (MOCVD) in a close coupled showerhead chamber. The AlSiO deposition temperature was 700 °C, and the TMAl, Si2H6, and O2 flows were 3.2 μmol/min, 3.2 μmol/min, and 4.4 mmol/min, respectively. AlSiO with various thicknesses (10 nm, 20 nm, and 30 nm) were deposited on three different Ga2O3 samples treated by UV-ozone followed by an HF dip. This improved surface preparation with a combination of UV-ozone and wet chemical treatment reduced near-interface traps resulting in a negligible hysteresis. The fast trap density was extracted to be 2.18×1011 cm-2, and the slow trap density excluding the contribution from fast traps was calculated to be 2.73×1011 cm-2. A net positive interface fixed charge of 1.56×1012 cm-2 was measured. The Dit was extracted accurately by accounting for dielectric bulk traps employing deep UV-assisted C-V method and physical models. An average interface state density of 6.63 ×1011 cm-2 eV-1 and AlSiO bulk trap density of 4.65×1017 cm-3 eV-1 were quantified, which is half of that for Al2O3 deposited by atomic layer deposition (ALD). In addition, a high dielectric breakdown field of ~7.8 MV/cm and more effective suppression of gate leakage were achieved on these devices compared with ALD-Al2O3 on similar metal-oxide-semiconductor (MOS) structures. The negligible hysteresis, lower interfacial trap density, low leakage current and high breakdown electric field achieved on AlSiO/Ga2O3 MOSCAPs reveals MOCVD AlSiO as a promising gate dielectric for high-performance Ga2O3 devices. [1] S. H. Chan et al., Jpn. J. Appl. Phys., vol. 55, no. 2, p. 021501, Feb. 2016. [2] D. Kikuta et al., J. Vac. Sci. Technol., vol. 35, no. 1, p. 01B122, Jan. 2017. [3] C. Gupta, et al., IEEE Electron Device Lett., vol. 38, no. 11, pp. 1575–1578, Nov. 2017. [4] I. Sayed et al., Appl. Phys. Lett., vol. 115, no. 17, p. 172104, Oct. 2019.

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High-Speed Two-Dimensional Solid-State Non-Volatile Memory Based on Electric Double Layer Gating Using a Monolayer Electrolyte

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Multi-level operation in VO2 resistive switching devices

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High-Speed Two-Dimensional Solid-State Non-Volatile Memory Based on Electric Double Layer Gating Using a Monolayer Electrolyte

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Multi-level operation in VO2 resistive switching devices

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