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Magnetic random access memory (MRAM) with its inherent non-volatility is believed to address the large stand-by energy issues in the present memory hierarchy [1]. In recent years, the spin-transfer torque (STT)-MRAM has gradually matured and started to appear in the market. Typically, STT writing of perpendicular magnetic tunnel junction (pMTJ) is limited to a few nanoseconds. This is because STT is collinear and competing with the intrinsic damping of the free-layer (FL), resulting in a long incubation delay [2] and large energy consumption.&lt;br/&gt;    To mitigate STT limitations, spin-orbit torque (SOT) and voltage control of magnetic anisotropy (VCMA) were proposed as alternative MRAM writing mechanisms. SOT is able to switch the FL of a pMTJ by injecting an in-plane current in an adjacent SOT layer, which enables a three-terminal cell structure with energy-efficient and reliable sub-ns writing capabilities [3]. On the other hand, VCMA promises significant advances toward low-power MRAM. The electronic-based VCMA effect can instantly modify the perpendicular magnetic anisotropy (PMA) of the FL to induce precessional switching at GHz rates and ultra-low energy consumption (fJ) [4]. However, both mechanisms also present technological challenges. The challenges for SOT are currently related to the density and write efficiency: the 2-transistor 1-MTJ cell structure limits the array density, and the SOT write current remains larger than for STT-MRAM, which imposes a large selector transistor to accommodate its write current. For VCMA, the write margin is small, and is subject to the variations in VCMA coefficient and field amplitudes, making write control difficult in dense arrays. Further, a large VCMA effect (&amp;gt;1000fJ/Vm) is mandatory to avoid compromising retention in sub-30nm pMTJ, which remains as a major challenge as typical values in pMTJs are 30-60 fJ/Vm at device level [5].&lt;br/&gt;    To overcome the above-cited limitations and to combine the best of these two approaches, voltage-gate assisted spin-orbit torque (VGSOT)-MRAM concept [Fig. 1(a)] has been proposed [6]. In this work, we report on VGSOT switching properties in pMTJ, integrated with our 300mm SOT-MRAM platform [3]. The stack is composed of W(3.5nm)/CoFeB(1nm)/MgO(1.7nm, RA ~ 5kΩ&lt;sup&gt;.&lt;/sup&gt;μm&lt;sup&gt;2&lt;/sup&gt;)/RL/SAF, where the thick MgO ensures pure VCMA gate control without STT contribution. We use an electrical scheme that allows for individual control over SOT/gate pulse amplitudes (&lt;i&gt;V&lt;sub&gt;SOT&lt;/sub&gt;&lt;/i&gt;/&lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt;), and variable pulse duration (&lt;i&gt;t&lt;sub&gt;p&lt;/sub&gt;&lt;/i&gt;). Fig. 1(b) shows exemplary SOT switching probability (&lt;i&gt;P&lt;sub&gt;sw&lt;/sub&gt;&lt;/i&gt;) curves under different &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt;, at &lt;i&gt;t&lt;sub&gt;p&lt;/sub&gt;&lt;/i&gt; = 0.4ns. We observe a clear decrease (increase) in &lt;i&gt;V&lt;sub&gt;SOT&lt;/sub&gt;&lt;/i&gt; under &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt; of 1V (-1V) for both AP-P and P-AP transitions. The critical switching voltage, defined at &lt;i&gt;P&lt;sub&gt;sw&lt;/sub&gt;&lt;/i&gt; = 50%, is converted into the critical switching current (&lt;i&gt;I&lt;sub&gt;c&lt;/sub&gt;&lt;/i&gt;) and plotted as a function of 1/&lt;i&gt;t&lt;sub&gt;p&lt;/sub&gt;&lt;/i&gt; in Fig. 1(c). It shows a typical linear scaling, i.e. &lt;i&gt;I&lt;sub&gt;c&lt;/sub&gt;&lt;/i&gt; = &lt;i&gt;I&lt;sub&gt;c0&lt;/sub&gt;&lt;/i&gt; + &lt;i&gt;q&lt;/i&gt;/&lt;i&gt;t&lt;sub&gt;p&lt;/sub&gt;&lt;/i&gt; in the sub-ns regime for all gate values [7], where &lt;i&gt;I&lt;sub&gt;c0&lt;/sub&gt;&lt;/i&gt; is the intrinsic critical current and &lt;i&gt;q&lt;/i&gt; indicates the nucleation energy for magnetization reversal. The linear dependences of &lt;i&gt;I&lt;sub&gt;c0&lt;/sub&gt;&lt;/i&gt; and &lt;i&gt;q&lt;/i&gt; on &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt; [Fig. 1(d)] reflect the direct modification of PMA upon &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt; applications and the change of nucleation energy, respectively. We report here a 25% reduction in &lt;i&gt;I&lt;sub&gt;c&lt;/sub&gt;&lt;/i&gt; under &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt; = 1V, which corresponds to a 45% reduction in total switching energy to 30fJ at 0.4ns. We further demonstrate that VGSOT offers reliable sub-ns switching with a low write error rate (&amp;lt;10&lt;sup&gt;-5&lt;/sup&gt;) and that VGOST-pMTJ is highly durable against large read/write stresses (&amp;gt;10&lt;sup&gt;12&lt;/sup&gt;)&lt;br/&gt;    Finally, we benchmark the VGSOT performance at the 5nm technology node against other embedded memory technologies to highlight the VGSOT benefits. It reveals that VGSOT-4MTJ design can reduce the effective cell area to &amp;lt;0.5x of the high-density SRAM at minimal performance degradation. Meanwhile, the constrain of achieving challenging material parameters for VCMA-MTJ (ξ &amp;gt; 1000fJ/Vm) and SOT-MTJ (θ&lt;sub&gt;SH&lt;/sub&gt; &amp;gt; 1.5) can be relaxed to reasonable values: ξ = 300fJ/Vm and θ&lt;sub&gt;SH&lt;/sub&gt; = 0.45. Our study shows the great potential of this VGSOT approach for fast, dense and low power embedded memory applications.

**References:**

[1] B. Dieny et al., Nat. Electron. 3, pp. 446–459 (2020)&lt;br/&gt;[2] T. Devolder et al., Phys. Rev. Lett. 100, 057206 (2008)&lt;br/&gt;[3] K. Garello et al., IEEE VLSI Circ., pp. 81-82 (2018)&lt;br/&gt;[4] Y. C. Wu et al., IEEE VLSI Tech., TMFS.4 (2020)&lt;br/&gt;[5] C. Grezes et al., IEEE Magn. Lett. 8, 3102705 (2017)&lt;br/&gt;[6] H. Yoda et al., IEEE IEDM, pp. 27.6.1-27.6.4 (2016)&lt;br/&gt;[7] K. Garello et al., Appl. Phys. Lett. 105, 212402 (2014)

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/704e6e8a749f9a7c8eea400c0ddf393c.jpg)
Fig. 1. (a) Illustration of the VGSOT writing scheme. (b) SOT switching probability (&lt;i&gt;P&lt;sub&gt;sw&lt;/sub&gt;&lt;/i&gt;) as a function of &lt;i&gt;V&lt;sub&gt;SOT&lt;/sub&gt;&lt;/i&gt; under different &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt; at &lt;i&gt;t&lt;sub&gt;p&lt;/sub&gt;&lt;/i&gt; = 0.4ns. (b) Critical SOT switching current and current density at &lt;i&gt;P&lt;sub&gt;sw&lt;/sub&gt;&lt;/i&gt; = 50% as a function of 1/&lt;i&gt; t&lt;sub&gt;p&lt;/sub&gt;&lt;/i&gt;, showing typical linear scaling for all &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt;. (c) &lt;i&gt;I&lt;sub&gt;c0&lt;/sub&gt;&lt;/i&gt; and &lt;i&gt;q &lt;/i&gt;as a function of &lt;i&gt;V&lt;sub&gt;g&lt;/sub&gt;&lt;/i&gt;.



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 Voltage-Gate Assisted Spin-Orbit Torque MRAM for High-Density and Low Power Embedded Applications INVITED

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Magnetic random access memory (MRAM) with its inherent non-volatility is believed to address the large stand-by energy issues in the present memory hierarchy [1]. In recent years, the spin-transfer torque (STT)-MRAM has gradually matured and started to appear in the market. Typically, STT writing of perpendicular magnetic tunnel junction (pMTJ) is limited to a few nanoseconds. This is because STT is collinear and competing with the intrinsic damping of the free-layer (FL), resulting in a long incubation delay [2] and large energy consumption. To mitigate STT limitations, spin-orbit torque (SOT) and voltage control of magnetic anisotropy (VCMA) were proposed as alternative MRAM writing mechanisms. SOT is able to switch the FL of a pMTJ by injecting an in-plane current in an adjacent SOT layer, which enables a three-terminal cell structure with energy-efficient and reliable sub-ns writing capabilities [3]. On the other hand, VCMA promises significant advances toward low-power MRAM. The electronic-based VCMA effect can instantly modify the perpendicular magnetic anisotropy (PMA) of the FL to induce precessional switching at GHz rates and ultra-low energy consumption (fJ) [4]. However, both mechanisms also present technological challenges. The challenges for SOT are currently related to the density and write efficiency: the 2-transistor 1-MTJ cell structure limits the array density, and the SOT write current remains larger than for STT-MRAM, which imposes a large selector transistor to accommodate its write current. For VCMA, the write margin is small, and is subject to the variations in VCMA coefficient and field amplitudes, making write control difficult in dense arrays. Further, a large VCMA effect (&gt;1000fJ/Vm) is mandatory to avoid compromising retention in sub-30nm pMTJ, which remains as a major challenge as typical values in pMTJs are 30-60 fJ/Vm at device level [5]. To overcome the above-cited limitations and to combine the best of these two approaches, voltage-gate assisted spin-orbit torque (VGSOT)-MRAM concept [Fig. 1(a)] has been proposed [6]. In this work, we report on VGSOT switching properties in pMTJ, integrated with our 300mm SOT-MRAM platform [3]. The stack is composed of W(3.5nm)/CoFeB(1nm)/MgO(1.7nm, RA ~ 5kΩ.μm2)/RL/SAF, where the thick MgO ensures pure VCMA gate control without STT contribution. We use an electrical scheme that allows for individual control over SOT/gate pulse amplitudes (VSOT/Vg), and variable pulse duration (tp). Fig. 1(b) shows exemplary SOT switching probability (Psw) curves under different Vg, at tp = 0.4ns. We observe a clear decrease (increase) in VSOT under Vg of 1V (-1V) for both AP-P and P-AP transitions. The critical switching voltage, defined at Psw = 50%, is converted into the critical switching current (Ic) and plotted as a function of 1/tp in Fig. 1(c). It shows a typical linear scaling, i.e. Ic = Ic0 + q/tp in the sub-ns regime for all gate values [7], where Ic0 is the intrinsic critical current and q indicates the nucleation energy for magnetization reversal. The linear dependences of Ic0 and q on Vg [Fig. 1(d)] reflect the direct modification of PMA upon Vg applications and the change of nucleation energy, respectively. We report here a 25% reduction in Ic under Vg = 1V, which corresponds to a 45% reduction in total switching energy to 30fJ at 0.4ns. We further demonstrate that VGSOT offers reliable sub-ns switching with a low write error rate (&lt;10-5) and that VGOST-pMTJ is highly durable against large read/write stresses (&gt;1012) Finally, we benchmark the VGSOT performance at the 5nm technology node against other embedded memory technologies to highlight the VGSOT benefits. It reveals that VGSOT-4MTJ design can reduce the effective cell area to &lt;0.5x of the high-density SRAM at minimal performance degradation. Meanwhile, the constrain of achieving challenging material parameters for VCMA-MTJ (ξ &gt; 1000fJ/Vm) and SOT-MTJ (θSH &gt; 1.5) can be relaxed to reasonable values: ξ = 300fJ/Vm and θSH = 0.45. Our study shows the great potential of this VGSOT approach for fast, dense and low power embedded memory applications.

**References:**

[1] B. Dieny et al., Nat. Electron. 3, pp. 446–459 (2020) [2] T. Devolder et al., Phys. Rev. Lett. 100, 057206 (2008) [3] K. Garello et al., IEEE VLSI Circ., pp. 81-82 (2018) [4] Y. C. Wu et al., IEEE VLSI Tech., TMFS.4 (2020) [5] C. Grezes et al., IEEE Magn. Lett. 8, 3102705 (2017) [6] H. Yoda et al., IEEE IEDM, pp. 27.6.1-27.6.4 (2016) [7] K. Garello et al., Appl. Phys. Lett. 105, 212402 (2014)

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/704e6e8a749f9a7c8eea400c0ddf393c.jpg)
Fig. 1. (a) Illustration of the VGSOT writing scheme. (b) SOT switching probability (Psw) as a function of VSOT under different Vg at tp = 0.4ns. (b) Critical SOT switching current and current density at Psw = 50% as a function of 1/ tp, showing typical linear scaling for all Vg. (c) Ic0 and q as a function of Vg.

technical paper

The perpendicular Spin-Transfer-Torque Magnetic Random Access Memory (p-STT-MRAM) is one of the most promising emerging non-volatile memory technologies. As these devices are limited by their thermal stability factor at technological nodes smaller than 20 nm, their downsize capability is compromised. Indeed, as the device shrinks, there is a decrease in thermal stability due to a decrease in the total interfacial perpendicular anisotropy energy proportionally to the cell area. This decrease significantly reduces the retention time of the memory [1-3]. A promising solution to this problem relies on taking advantage of the shape anisotropy of the storage layer by increasing its thickness to values larger than its diameter. The shape anisotropy becomes out-of-plane, with strength proportional to the large volume of the thick cell, bringing an additional robust and tunable source of perpendicular anisotropy on top of the interfacial perpendicular anisotropy. These two sources of anisotropy allow to extend the downsize scalability of STT-MRAM towards sub-20 nm technological nodes [4, 5]. However, the storage layer thickness also affects the writing operation of the cell and should be examined. In this work, the magnetization reversal mechanism of the PSA-STT-MRAM induced by STT was numerically studied. Micromagnetic simulations were carried out (with and without the effect of thermal fluctuations), enabling the identification of different modes of magnetization reversal in this memory. An initial study comprises pillars with aspect-ratios (AR) between 0.8 and 3, with a fixed diameter of 20 nm. It was shown that, for an AR smaller than 1, the mechanism of reversal follows a macrospin-like reversal. When increasing the AR, a non-coherent reversal develops, which evolves from a buckling-like reversal to a transverse-domain wall nucleation-propagation at higher aspect ratios. This latter mode of reversal is associated with the slowing down of the switching dynamics, an effect which worsens as the layer thickness is increased [Fig. 1]. The inverse of the switching time follows a linear relationship with the applied voltage, a law conserved when considering thermal fluctuations. This demonstrates that, even though the nucleation process is assisted by thermal fluctuations, the reversal is controlled by the STT. Changing both the diameter and the thickness but maintaining a thermal stability factor of around 80 it is observed that the minimum voltage to reverse the storage layer increases [Fig. 2]. We interpret as the weakening influence of the strong interfacial STT of tunnelling electrons. This comes along with a transition from a macrospin-like reversal to a buckling-like reversal when AR is increased, despite the thermal stability value is in the same range. This study shows the possibility to obtain a macrospin-like reversal at low applied voltages at sub-20 nm magnetic tunnel junctions. With their switching time of the order of tens of ns, these PSA-STT-MRAM are not fast-enough memories suitable for Cache application but should be functional for dense DRAM type of applications. Also, the junction Resistance x Area product must be lowered compared to conventional STT-MRAM to maintain the write voltage significantly below the barrier breakdown voltage.

**References:**

[1] C. Yoshida et al, Jpn. J. Appl. Phys. 58, SBBB05 (2019). [2] H. Sato et al, Jpn. J. Appl. Phys. 58, 0802A6 (2017). [3] L. Thomas et al, J. Appl. Phys. 115, 172615 (2014). [4] N. Perrissin et al, Nanoscale 10, 12187-12195 (2018) [5] K. Watanabe et al, Nat. Com. 9, 663 (2018).

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/f528241113b078615ca57fd5629207ff.jpg)
Fig 1: Time traces of the mean reduced magnetization 〈mz〉for different pillar thicknesses for an applied voltage of -3 V.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/67e3ba17811e7244cfa1ee6d319e6030.jpg)
Fig 2: Voltage dependence of the time to reverse 50% of the magnetic layer (switching time - τswitch) for different pillar sizes.

 Magnetization reversal driven by spin-transfer-torque in sub-20 nm perpendicular shape anisotropy magnetic tunnel junctions

The rising demand for high efficiency computing has driven development pursuits to identify a “beyond-CMOS” dimensionally scalable logic technology. Superconducting technologies (such as reciprocal quantum logic) offer a solution to this growing challenge; however, these systems require a compatible low temperature memory solution that is power efficient, dense, and fast. To meet this need, Josephson magnetic random access memory (JMRAM) is being pursued. [1-4] In its simplest form, JMRAM combines superconducting electrodes (S) with a ferromagnetic (F) spin valve to form magnetic barrier Josephson Junctions (MJJs). JMRAM optimization requires that magnetic layers exhibit single domain switching with abrupt magnetization reversal and low switching fields, at cryogenic temperatures. JMRAM requirements are further complicated as materials selection and thicknesses must allow MJJs to carry a sufficient critical current (Ic), consistent with low error rate operation, at 4K. In this work, we show fundamental low temperature (T) magnetic and Ic responses of a model S/F/S system – Nb/CoFeB/Nb – and relate this to roughness effects that arise in ultra-thin film systems. Ultra-thin CoFeB films (6-13 Å) deposited onto 1500 Å Nb/50 Å Cu and 1500 Å Nb/ML (ML = (10 Å Cu/5 Å Nb)6/10 Å Cu) and capped with 50 Å Cu/500 Å Nb have been examined structurally, magnetically and electrically. Prior work has shown improved magnetic switching and decreased surface roughness with the incorporation of the ML structure as a buffer under the ferromagnetic layer. [4] The film thicknesses and amorphous structure were confirmed with x-ray reflectivity and diffraction. The magnetic character was probed at 300 K and compared to the 10 K response. MJJ Ic was measured at 4 K. Here, CoFeB films exhibit low reversal fields at 300 K (Fig 1a), analogous to MRAM devices that utilize CoFeB as a soft ferromagnet with a MS value ~ 1525kA/m. Patterned films, measured at 10 K, show an expansion of the magnetic hysteresis (Fig 1b). Incorporation of the ML buffer shows reduced coercivity (Fig. 1a, T = 300 K) and improved squareness (Fig. 1b, T = 10 K). In electrical devices, the Ic through the CoFeB layer decays exponentially with increasing CoFeB thickness and shows a dip in Ic at 8 Å (Fig 2), characteristic of a change in the equilibrium Josephson phase in an S/F/S structure, the “0 – π” thickness. While the ultimate objective of these efforts is to achieve a cryogenic memory solution, the work described here probes the fundamental properties of low T magnetics and S/F/S character of a candidate material for this emerging technology.

**References:**

[1] IM Dayton, MG Loving et al. “Experimental Demonstration of a Josephson Magnetic Memory Cell With a Programmable pi-Junction” IEEE Magnetics Letters 9, 1 (2018) [2] A. Herr and Q. Herr "Josephson Magnetic Random Access Memory System and Method". US Patent US20110267878 A1, 30 April 2010 . [3] MG Loving, TF Ambrose, Ferrimagnetic/ferromagnetic exchange bilayers for use as a fixed magnetic layer in a superconducting-based memory device, US Patent App. 16/256,547, 2020 [4] TF Ambrose, MG Loving, Repeating alternating multilayer buffer layer, US Patent No: 10879447 B2, 29 December 2020

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/59d7948c169f880570f521dd13750027.jpg)
Fig 1: Comparison of a) room temperature (T = 300 K) blanket film measurements and b) low temperature (T = 10 K) patterned array magnetic switching. Both data sets show improved magnetic performance with the ML buffer.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/a357a3de541197ac98981bfa3a030c17.jpg)
Fig. 2: Comparison of the buffer layer impact on Ic vs. CoFeB thickness, in Angstroms

 Magnetic Reversal and Critical Current Transparency of CoFeB Superconductor-Ferromagnet-Superconductor Heterostructures

The current information technology has been relied on von Neumann type computation [1]. In order to manage the recent digital universe and big data, it is essential to investigate alternative technologies to sustain the development in computation. Among them, neuromorphic computation has been attracting intensive studies using the current complementary metal oxide semiconductor (CMOS) architecture and beyond in the last decade to mimic the functionality and operation of a synapse in a brain. A promising synapses operation has been demonstrated via the stochastic operation of a magnetic tunnel junction (MTJ) [2]. However another important feature of a synapse, memory potentiation, has been overlooked to date. In this study we have demonstrated memory functionality via current-induced annealing in a giant magnetoresistive (GMR) junction with ferromagnetic Heusler alloy films. A GMR junction consisting of Cr (3)/W (10)/Co2FeAl0.5Si0.5 (CFAS) (10)/Ag (3)/CFAS (2.5)/Ru (3) (thickness in nm) was fabricated as an artificial synapse with achieving a low resistance-area product for low power consumption. Here we recently reported the reduction in the crystallisation temperature by promoting layer-by-layer growth on a (110) surface [3], of which is comparable with Joule heating induced by a controlled current introduction. The multilayered stack was grown on a thermally oxidised Si substrate using a high target utilisation sputtering system (PlasmaQuest, HiTUS) at room temperature. The stack was patterned into a nanopillar junction using a combination of electron-beam lithography and Ar-ion milling. The seed layer, Cr/W, was patterned into a bottom electrode with a width of 100-200 nm. Just above the bottom Heusler-alloy layer was patterned into a nanopillar with a diameter between 80 and 200 nm, followed by the patterning of a top electrode with Ti/Au. The fabricated nanopillars were measured using a probe station (HiSOL, HMP-400 SMS) with a conventional four-terminal method with a constant current source (Keithley, 2400) and a nanovoltmeter (Keithley, 2182a). The resistance changes were measured after a series of current pulse applications of 500 µA up to 5 mA for 100 µs up to 500 µs. Little change was observed at 500 μA, which was used for GMR measurements, while monotonic resistance change was measured above 1 mA with the repetition of 100 µs pulse introduction, confirming the current-induced crystallisation of CFAS(110) and the associated change in the resistivity. The Heusler-alloy crystallisation was then observed using transmission electron microscope (TEM; JEOL, JEM-2200FS) by thinning with focused ion beam (FIB, FEI, Nova 200 Dual Beam). The crystallinity of the CoFeAl0.5Si0.5 has been confirmed using nanobeam, which shows some CFAS(220) diffraction spots within polycrystalline ring feature. TEM imaging confirmed CFAS was partially crystallised with maintaining a smooth interface of &lt; 1 nm roughness in the GMR junction. Due to the nature of a simple electrical current introduction employed in this study, the GMR junction does not require post-annealing processes but it can stores the operation cycle permanently as the change in the resistivity. Hence such current-induced crystallisation can be used in a neuromorphic node network, which can revolutionalise solid state memory.

**References:**

[1] B. V. Benjamin, P. Gao, E. McQuinn, S. Choudhary, A. R. Chandrasekaran, J.-M. Bussat, R. Alvarez-Icaza, J. V. Arthur, P. A. Merolla and K. Boahen, K. Neurogrid Proc. IEEE, vol. 102, p. 699 (2014). [2] J. Grollier, D. Querlioz, and M. D. Stiles, Proc. IEEE, vol. 104, p. 2024 (2016). [3] J. Sagar, L. R. Fleet, M. Walsh, L. Lari, E. D. Boyes, O. Whear, T. Huminiuc, A. Vick and A. Hirohata, Appl. Phys. Lett., vol. 105, p. 032401 (2014).

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/e0321b566666d32b22e641e5de173bf6.jpg)
Fig. 1 Evolution of magnetic moment and grain size of the Heusler alloy films and their corresponding crystalline structures.

 Current-Induced Crystallisation in Heusler Alloy Films

Introduction: Double CoFeB/MgO interface perpendicular MTJ has become the de facto standard technology of current STT-MRAM. However, there are still issues for high density memory application and high reliable application including Automobile applications. Furthermore, achievement of high speed and high endurance features, in the other words, high speed SRAM replacement is still challenging for STT-MRAM, because of its tradeoff relationship among the retention, endurance, and operational speed. Recently, Spin Orbit Torque (SOT) devices have been intensively researched and developed because SOT devices have the potential to achieve high speed and high endurance. To realize the practical use of SOT-MRAM for LSI applications, these issues must be addressed. This invited paper reviews our recent progresses in STT-MTAM, SOT-MRAM and Nonvolatile AI processors with CMOS/MTJ hybrid technology. The STT-MRAM and SOT-MRAM as NV working memory and AI processors as these applications are particularly suitable for future IoT / AI systems that require ultra-low-power and high-performance computing at the same time. 128Mb STT-MRAM and Quad interface MTJ technology: We developed novel damage control integration process technologies including new low-damage MgO deposition process, low-damage RIE process, and low temperature SiN-cap process. By applying the developed damage control integration process technologies to double interface p-MTJ fabrication, TMR ratio, thermal stability factor, and switching efficiency of Double p-MTJ were successfully improved. Moreover, it was shown that despite the significant increase in thermal stability factor, the endurance of the fabricated Double p MTJs was over 1010. Finally, with our double-interface p-MTJ technology and novel damage control integration process technologies, fabricated 128Mb STT-MRAMs successfully achieved 14ns/7ns write speed at Vdd of 1.2V/1.8V, respectively. Next, for further scaling of STT-MRAM, we proposed novel Quad-interface p-MTJ technology which brings forth an increase of thermal stability factor compared with conventional Double-interface p-MTJ technology. We successfully fabricated the quad-interface MTJ using 300mm process based on the damage control integration process. The fabricated Quad p-MTJs achieved an enhancement of switching efficiency in addition to an approximately two times larger thermal stability factor without degradation of TMR ratio. The developed Quad p-MTJ technology will become an essential technology for the scaling of the STT-MRAM beyond 20nm without changing material and process sets from mass-production STT-MRAM. Moreover, the high reliable Quad p-MTJ technology with enough thermal stability factor is suitable for Automobile applications that require high temperature operation such as 150○C. Field-free canted SOT-Device with 350ps write speed and its SOT-MRAM: To realize practical use of SOT-MRAM for LSI applications, we demonstrated 55 nm-CMOS/SOT-device hybrid MRAM cell with magnetic field free writing for the first time. For field free writing, we developed canted SOT device under 300 mm BEOL process with 400°C thermal tolerance. In addition, we developed its advanced process as follows; PVD process of SOT channel layer for high spin Hall angle under 400°C thermal tolerance, low damage RIE technology for high TMR/thermal stability factor, and ultra-smooth surface metal via process under SOT device to reduce contact resistance. By using the developed technologies, our canted SOT devices achieved fast write speed of 0.35 ns without magnetic field, an enough thermal stability factor of 70 for non-volatile memory (over 10 years retention), and a high TMR ratio of 167%, simultaneously. Moreover, we fabricated a field free canted SOT-MRAM cell with 55 nm CMOS technology and demonstrated its write/read performance. These technologies will open to high speed write non-volatile memory such as 1 level cache application of many kinds of application processors. CMOS/MTJ hybrid AI Processor for low power application: Focusing on the indispensable nearest neighbor search (NNS) function of the brain, we developed a nonvolatile object recognition processor with NSS full-adaptive to any data format, employing nonvolatile memories base on our p-MTJ. The developed object recognition processor was fabricated under 90nm-CMOS/70nm-MTJ hybrid process on 300mm-wafer. The 4-Transistors & 2-MTJs type memory cells were adopted to completely eliminate standby power. Moreover, we successfully developed a self-directed power-gating technique leveraging the non-volatility, high access speed and unlimited endurance features of the p-MTJs. This developed self directed power-gating technique was employed to shut down idle circuit blocks during not only the standby periods but also the full operation periods. The measured peak operation power consumption of the prototype chip was only 130μW and can be further optimized corresponding to the format of reference data. Compared to the latest conventional researches, the significant improvements of both power performance (about 2-3 order reduction) and circuit density (about 2 order improvement) were achieved.

**References:**

[1] S. Ikeda et al., Nat. Mater. 9, 721 (2010). [2] T. Endoh et al., 2011 International Electron Device Meeting (IEDM), 2011. 34 [3] H. Sato et al., Appl. Phys. Lett. 101, 022414 (2014). [4] T. Saito et al., IEEE T-Magn. 54, 3400505 (2018). [5] H. Sato et al., IEDM 2018, p. 608. [6] K. Lee et al., IEDM 2018, p. 604. [7] Y. J. Song et al., IEDM 2018, p. 416. [8] C. Park et al., VLSI 2018, p. 185. [9] O. Golonzka et al., IEDM 2018, p. 412. 6 [10] C. Park et al., VLSI 2018, p. 185. [11] T. Endoh, IEEE ISCASS2018. (Invited) [12] K. Nishioka et al., VLSI 2019, T11-4; IEEE T-ED 67, 995 (2020). [13] S. Fukami et al., VLSI 2016, T61. 10 [14] H. Honjo et al, IEDM 2019, 28.5.1. [15] T. Endoh, MRAM Development Day 2019 (Invited) [16] T. Endoh, 2020 International Solid-State Circuits Conference (ISSCC) (Invited) [17] T. Endoh et al, VLSI Symp. 2020 (Invited) [18] T. Endoh, Tutorial of IEDM2020 (Invited)

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/4ab86aad73439f39476f104f23a8eb59.jpg)
Fig. 1: (a) developed 128Mb STT-MRAM. (b) photograph of its subarray. (c) Shmoo plot of subarray in 128Mb STT-MRAM. (d) Switching efficiency as a function of CD for the Quad- and Double-interface MTJs.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/b8abc4d21c732c328f6998e190bbd9cb.jpg)
Fig. 2: (a) Developed AI object recognition processor with 90nm-CMOS/70nm-MTJ. (b) Further performance comparisons of the operation power efficiency and circuit density.

 Advanced MTJ and SOT Technology for AI and Automobile applications INVITED

As the crucial device element for next-generation cache and edge computing technologies, the magnetic tunnel junction (MTJ) has been widely studied with recent focus towards using spin-orbit torque (SOT) to switch the free layer magnetization. Writing the MTJ using SOT approach is attractive, because it can increase the junction endurance as switching current path does not go through the tunneling barrier. In this work, we aim to enhance the SOT switching efficiency in the MTJ through various interlayer insertion designs in the free layer. Our study is carried out using in-plane MTJ (IP-MTJ), which has been demonstrated that no external magnetic field is required for SOT switching [1]. We fabricated W underlayer-based IP-MTJs, and investigate how the insertion layer between the W and CoFeB free layer affects the switching current density of the MTJ. Interestingly, with the insertion of ultra-thin layers such as MgO, Ru and TiW, the switching current drops significantly with the MgO insertion offering ~70% of reduction. Here, standalone 3-terminal IP-MTJ devices of elliptical sizes 300 nm x 600 nm are fabricated using Canon X5 stepper lithography on 8 inch Si wafers. We measure the pulse current switching loops with our home-built probe station [2]. Without insertion layer, the switching current is ~11.9 mA, equivalent to ~1.9x1011 A/cm2. The large value of switching current density is because of the dramatic reduction in the spin Hall angle (SHA) of W underlayer after annealing at 330°C, which also leads to a structural phase change to α-W. While the introduction of an insertion layer universally reduces the current density. The MgO interlayer reduces it by more than 3 times making it superrior for insertion layer selection. To understand it better, we performed spin-torque ferromagnetic resonance (ST-FMR) measurement [3] to determine the damping constant, spin Hall angle, and effective saturation magnetization (Ms_eff). A representative example of ST-FMR spectra for MgO insertion layer is shown in Fig. 1. We found the thin insertion layer has little influence on the damping constant, but some modifications in Ms_eff and SHA are found, which can be correlated with the switching current reduction results. Further investigations on the role of insertion layer thickness are ongoing and are expected to reveal the optimal insertion layer for SOT current reduction.

**References:**

[1] L. Liu, C.F. Pai, Y. Li et al., Science, Vol. 336, p.555 (2012) [2] J. Lourembam, J. Huang, S.T. Lim et al., AIP Adv., Vol. 8, p.055915 (2017) [3] L.S. Huang, S.K. He, Q.J. Yap et al., Appl. Phys. Lett., Vol. 113, p.022404 (2018)

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/ad011acedbe5cfe942648e452a3ab9a6.jpg)
Fig. 1 Field sweep ST-FMR spectra of W/MgO/CoFeB/MgO film. The RF frequency varies from 7 to 20 GHz.

 Effect of insertion layer on reducing switching current density in spin-orbit torque magnetic tunnel junction

Spin-orbit torque (SOT) induced magnetic switching has attracted an extensive interest due to its potential high efficiency in terms of switching time and power consumption [1]. Chiral domain wall (DW) motion driven by SOT in nanowires in the presence of Dzyaloshinskii–Moriya Interaction (DMI) at interfaces between HM and FM layers has shown a great potential for applications to racetrack memory devices [2]. One potential advantage of DW driven switching is that multi-level states can be obtained by controlling the position of the DW across a nanostructure such as wires or dots. As such, domain wall Memristors and the possibility to use DWs motion as synapses [3] have been recently demonstrated. Here, we study SOT driven multi-level states in Hall bars based on W-CoFeB-MgO structures by reducing locally the perpendicular magnetic anisotropy through He+ ion irradiation across a mask [4]. The structure of the investigated samples is W (4 nm)/Co20Fe60B20 (0.6 nm)/MgO (2 nm)/Ta (3 nm). The films were then patterned into Hall bars consisting in 20 μm wide and 140 μm long wires including 2 Hall crosses with 5 μm wide pads. As shown in previous studies [6], light He+ ion irradiation induced interface intermixing can be used to finely tune Ms, interface anisotropy and DMI in CoFeB-MgO structures. One of the Hall cross was then subsequently irradiated through a mask by He+ ions with an energy of 15 keV at a fluence of 1×1019 ions/m2 to reduce locally the perpendicular anisotropy Keff. Anomalous Hall Effect measurements combined with Kerr microscopy indicate that the SOT switching process is dominated by domain wall nucleation in the irradiated region followed by rapid domain propagation to switch the irradiated area (figure 1). The reduction of Keff by 20% under ion irradiation is accompanied by a large reduction of the switching current from 4.07 to 1.68 MA/cm2 under an in-plane 50 mT field; The switching current is determined by the threshold current to induce DW nucleation as checked by Kerr microscopy. As Keff is lowered in the irradiated Hall bar, the energy barrier to induce DW nucleation by SOT is also reduced. Due to the strong pinning of the DW at the transition between the irradiated and the non-irradiated region as evidenced by Kerr microscopy, we observe an intermediate Hall resistance state between the 2 saturated states (Figure 2). The possibility to increase the number of intermediate states by designing different value of perpendicular anisotropy through He+ ion irradiation paves the way towards efficient neuromorphic and memristor devices where the nucleation, motion and pinning can be tailored.

**References:**

[1] M. Cubukcu, et al, IEEE Transactions on Magnetics 54, 9300204 (2018) [2] K. S. Ryu et al, Nat. Nanotechnol. 8, 527 (2013) [3] S. Lequeux, et al, Scientific Reports 6, 31510 (2016) [4] X.Zhao, Appl. Phys. Lett 116, 242401 (2020)

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/15951bba9072bcb7b7faba4b2ff3dd61.jpg)
 
Figure 1. Kerr images showing the SOT induced magnetization switching process of the Hall bar for an increasing current under a 50 mT in-plane magnetic field. The white dashed lines indicate the longitudinal wire and the transverse Hall voltage pads. The gray box corresponds to the irradiated area. The yellow arrow in (iv) shows the direction of domain wall motion.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/50371af00eff66ca4a5d33d727cefb07.jpg)
Figure 2. SOT switching curve for an irradiated Hall cross measured under 50 mT. States 1, 2, 3 correspond to down magnetization, intermediate state and up magnetization respectively

 Spin orbit torque driven multi-level switching in He+ irradiated W-CoFeB-MgO Hall bars with perpendicular anisotropy

In the last decade, spin-orbit torque (SOT) [1-3] has enabled us to electrically control spins of magnetic materials, which provides an idea manner to develop magnetic random-access memory (SOT-MRAM). One crucial step toward the SOT-MRAM is realization of magnetic tunnel junctions (MTJ) whose magnetic states can be switched by SOT at zero applied field. In our previous paper [4], we have realized field-free SOT switching of a perpendicular CoFeB film which coupled with another CoFeB film with in-plane magnetization via a Ta spacer. This structure composed by the perpendicular CoFeB, the in-plane CoFeB and the spacer Ta is entitled as the“T-Type” magnetic structure. Here, by using an in-plane CoFeB/Ta/perpendicular CoFeB T-type magnetic structure as a free layer, we have realized a MTJ switchable by SOT at the field-free condition (Fig. 1) [5]. The spacer layer Ta plays three roles. Besides of absorbing the B element during annealing process to improve TMR ratio, it also mediates exchange coupling and finally generates large enough SOT to drive sharp switching between the parallel and antiparallel states of the MTJ without any applied fields. This work could provide a useful stack with the T-type structure to realize field-free SOT-MRAM or logic devices.

**References:**

[1] I. M. Miron, K. Garello, G. Gaudin, P.-J. Zermatten, M. V. Costache, S. Auffret, S. Bandiera, B. Rodmacq, A. Schuhl, and P. Gambardella, Nature, 476, 189 (2011). [2] L. Liu, C. F. Pai, Y. Li, H. W. Tseng, D. C. Ralph, and R. A. Buhrman, Science, 336, 555–558 (2012) [3] L. Liu, O. J. Lee, T. J. Gudmundsen, D. C. Ralph, and R. A. Buhrman, Phys. Rev. Lett. 109, 096602 (2012) [4] W. J. Kong, C. H. Wan, X. Wang, B. S. Tao, L. Huang, C. Fang, C. Y. Guo, Y. Guang, M. Irfan, and X. F. Han, Nat. Commun. 10, 233 (2019) [5] W. J. Kong, C. H. Wan, C. Y. Guo, C. Fang, B. S. Tao, X. Wang, and X. F. Han, Appl. Phys. Lett. 116, 162401 (2020).

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/ab60392e9068d8cdd9d3b5c29751a49c.jpg)
Fig.1 (a) Schematics of a MTJ with the T-type magnetic structure as its synthetic free layer. (b) Out-of-plane and (c) in-plane hysteresis loops of the stack Sub//Ta(8)/ Co40Fe40B20(2)/Ta(1.3)/Co40Fe40B20(0.6)/MgO(2.5)/Co40Fe40B20(1.2)/Ta(5)/Ru(5 nm) to show a perpendicular layer and an in-plane layer in it. (d) The TMR ratio as a function of the Hz field and (e) Current-driven magnetization switching at +/-300 Oe and 0 field. The switching direction at zero field depends on the history of reducing field.

 All-electrical manipulation of magnetization in magnetic tunnel junction via spin–orbit torque

Spin-orbit torque magnetic RAM (SOT-MRAM) is affected by read disturbances due to spin current in the heavy metal layer that arises from spin-orbit interaction at the time of reading [1]. To resolve this issue, we have proposed a stabilized structure with a bi-directional read path, based on the idea that spin currents flowing in opposite directions on either side of the heavy metal layer cancel each other’s effects, that improves the read reliability of SOT-MRAM. We have already reported that this structure reduces the read disturbance [2]. In this study, we evaluated the movement of the magnetization of the free layer at the time of reading in a bi-directional read SOT-MRAM by using an LLG simulator. It was found that the read disturbance caused by SOT is removed in the free layer, as shown in Fig. 1 (a). In other words, the spin currents generated in opposite directions in the heavy metal layer directly affect the magnetization of the free layer, and the free layer functions as if it were two ferromagnets, whose balanced magnetizations cancel the read disturbance. To clarify this mechanism, Fig. 1 (b) shows the simulated magnetization for only the free layer at extremely large currents. The free layer is a ferromagnet magnetized in two opposite directions due to the central vortex magnetization, and the magnetization does not reverse to either side. (That is, it is not a mechanism in which the spin currents cancel themselves in both directions in the heavy metal layer.) Toward the realization of this bidirectional read SOT-MRAM structure, we evaluated the effect on the read disturbance of the size of the direction in which current flows through the heavy metal layer of an SOT structure. The device structure had an magnetic tunnel junction (MTJ) with two ferromagnets (cobalt), in which a pinned layer with a thickness of 3.5 nm and a free layer with a thickness of 1.5 nm sandwiched an insulating layer with a thickness of 1.0 nm, and a heavy metal layer (tungsten) with a thickness of 2.0 nm under the free layer. The magnetization of the two ferromagnetic layers directed toward the short side direction of the device, and the current passed from the pinned layer to both ends in the long side direction of the heavy metal layer. The width in the short side direction was uniformly 30 nm, and there were four device widths for the long side direction, i.e., 30 nm, 60 nm, 120 nm, and 180 nm. We evaluated the magnetization reversal probability of a conventional SOT-MRAM structure and the stabilized SOT-MRAM structure for a read time of 5 ns. Fig. 2 shows that the stabilized SOT-MRAM was about 6 to 10 times more effective than the conventional structure. In the conventional SOT-MRAM, the threshold current was proportional to the width of the device, whereas in the stabilized SOT-MRAM, the threshold current decreased as the width of device increased. The magnetization reversal of the conventional SOT-MRAM was strongly affected by the SOT disturbance due to the spin Hall effect, and the difference in thermal stability depending on the device size also had an influence. On the other hand, in the stabilized SOT-MRAM, the disturbance was canceled out at the free layer and only spin transfer torque in MTJ affected the magnetization reversal. Thus, we expected that the relationship between thermal stability and device size would have a large effect on magnetization reversal, but the result was contrary to that. These results indicate that the force exerted by the spin Hall effect on the magnetization of the free layer is relatively large and easy to act when the device is small. Therefore, a small device of the conventional SOT-MRAM tend to easily occur magnetization reversal, whereas in a smaller device of the stabilized SOT-MRAM, the effect on the magnetization of the free layer is strong enough to cancel the SOT disturbance and the magnetization reversal becomes more difficult. Acknowledgments This work was partly supported by a Grant-in-Aid for Scientific Research (19K04536) from Japan Society for the Promotion of Science.

**References:**

[1] H. Kazama and T. Kawahara, “Spin-Orbit Torque MRAM Read Reliability”, 2017 IEEE International Magnetics Conference (Intermag2017), DOI: 10.1109/INTMAG.2017.8007571, 2017. [2] Y. Kishi, K. Tabata, M. Ke, and T. Kawahara, "Evaluation of Read Disturbance Reduction Effect by Bi-directional Read on Ferromagnetic Material Properties of SOT-MRAM", ABSTRACT of IEEE/AIP 2020 Magnetism and Magnetic Materials Conference (MMM2020), O2-14, pp.434-435, 2020.

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/3e0ae5fa7997c288903464f85d3c9b8c.jpg)
Fig. 1 (a) Stabilized structure (bi-directional read) of SOT-MRAM device [1]. The blue arrows indicate the current directions. Two red circles in the free layer canceled the SOT disturbance. (b) Example of simulation results showing the movement of the magnetization in the free layer of the stabilized structure. We simulated with a two-layer structure consisting of a free layer and a heavy metal layer. A vortex magnetization is created in the middle, dividing the free layer. The two split ferromagnets are magnetized in opposite directions.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/7e606b44e402730cd84b8ea8cae483f6.jpg)
Fig. 2 Comparison of conventional and stabilized (bi-directional read) SOT-MRAM threshold currents for different X sizes of SOT structure for a read times of 5ns. In the SOT structure, two ferromagnetic layers (cobalt) sandwich an insulator, and a heavy metal layer (tungsten) is under the free layer; the current flows from the pinned layer to the long side of the heavy metal layer. The magnetization of the ferromagnetic layers are basically in the short-side direction, but the magnetization of the free layer is in any direction.

 Evaluation of Read Disturbance Reduction Effect by SOT-MRAM Bi-directional Read on Device Size Dependence

Spin-orbit torque (SOT) devices1 are promising candidates for the future magnetic memory landscape as they promise a low read disturbance, high endurance and low read error, in comparison to the spin-transfer torque devices. However, SOT memories are area intensive due to the requirement of two access transistors per bit2. Here, we report a SOT memory cell which has multiple bits sharing a common write channel. This enables twice the memory density compared to the conventional SOT-MRAM design. The shared write channel (SWC) design is shown in Fig. 1. Multiple bits share a common write path thereby reducing the need for two access transistors for every bit. With a single pulse of current, different combination of digital information can be written on all the bits on the shared path. SPICE circuit simulations were performed and the area per bit of the 32x32 SWC memory is found to be 0.0414 µm2 while that of the normal 2 transistor (T)-SOT memory is around 93% larger at 0.0801 mm2. However, an essential design requirement for SWC memory is programmable SOT device for which the direction of SOT can be toggled dynamically. With different polarities of SOTs for individual bits on a shared path, information such as ‘0101..’ and ‘1001..’ can be written. A SWC device with 2-bits is demonstrated using a Pt/Co device with a GdOx gate oxide (Fig. 2(a)). The direction/polarity of SOT in such a device can be toggled by modulating the oxygen content at the Pt/Co interface3, 4. This can be achieved by the application of gate voltage through the GdOx gate. As shown in Fig. 2(b), the multi-bit device can be programmed in different states so that all combination of digital information can be written using an unidirectional current pulse. Our prototype device paves a way towards a high density SOT MRAM architecture.

**References:**

 1. I. Mihai Miron, G. Gaudin, S. Auffret, et al. Nature Materials Vol. 9, p. 230 (2010). 2. R. Bishnoi, M. Ebrahimi, F. Oboril et al. in 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC) p. 700 (2014). 3. R. Mishra, F. Mahfouzi, D. Kumar et al. Nature Communications Vol. 10, p. 248 (2019). 4. X. Qiu, K. Narayanapillai, Y. Wu, et al. Spin–orbit-torque engineering via oxygen manipulation. Nature Nanotechnology Vol. 10, p. 333 (2015).

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/8c4ae1e6e475f27a9ef80e64dedab035.jpg)
Figure 1. A shared write channel based SOT design. Multiple bits share a common write channel, thereby reducing the need for dedicate write transistor for individual bits.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/d648fbc35ed503d00c3ea8b6a917580f.jpg)
Figure 2. (a) A Pt/Co/GdOx based 2-bit memory cell in which SOT polarity of individual bit can be programmed independently. (b) The two bits can be switched independently in different directions depending on the programmed SOT state. The blue switching curve represents normal SOT switching for a Pt device. The red switching curve is obtained after the application of negative gate voltage on the bit, which increases the oxygen content at the Pt/Co interface thereby changing SOT polarity to negative.

 Multi-bit Spin-orbit Torque Device for High Density MRAM

Demand for Artificial Intelligence (AI) has been growing due to their usefulness in commercial electronics as well as tackling global issues, such as a pandemic [1]. Current devices that perform AI rely on the conventional von Neumann architecture, which requires extensive programming and power [2]. Therefore, significant attention is dedicated to the brain-inspired neuromorphic computing (NC) as an alternative that is more power-efficient and a more suitable platform for AI [3]. Neuromorphic architecture consists of a network of interconnected synapses and neurons that mimic their biological counterparts [4]. Sengupta et al. have proposed a neuron design based on a domain wall device that uses a magnetic tunnel junction (MTJ) [5] at one end. The tunneling magnetoresistance (TMR) depends on the position of the DW. A current is required to move the domain wall forward or backward (integrate or leak functions respectively). In this work, we place emphasis on designing a domain wall (DW) based artificial neuron, which displays the leaky function without the requirement for a driving current. To achieve leaky function and self-reset process of neuron, we propose a domain wall device, which has an anisotropy field (Hk) gradient in the region of interest (ROI), as shown in Fig. 1(a). This anisotropy gradient is crucial in inducing the automatic returning motion of DW in the absence of current. The design is simulated using Mumax3, and the DW in the free layer nanowire (NW) is driven by spin-transfer-torque (STT). As shown in Fig. 1, current is first applied to propagate the DW towards the threshold position to “fire” the neuron device; current is subsequently removed and DW motion is observed. The micromagnetic parameters used here represent the magnetic properties of CoFeB film with a perpendicular magnetic anisotropy. The magnetic anisotropy constant (Ku) and saturation magnetization (Ms) are graded in ROI, so that Hk gradient is achieved. Some results are presented in Fig. 2(b), showing DW position vs time graph of the reference NW, without any gradient. One may notice that the DW does not return towards the initial position in these devices. Fig. 2(c) corresponds to a device with an Hk gradient. We can notice that the device enables natural return of the domain wall towards the starting position in the absence of current. This suggests that the device displays the leakage function, as well as the ability to reset after the neuron has fired. Fig. 2(d) corresponds to the same device as that of Fig. 2(c), except in this case, three current pulses are consecutively applied with a time interval of 60 ns. These results indicate that the neurons can function with a reset time of about 60 ns. The proposed design has potential applications for DW-based artificial neuron since it displays the integration and leakage functions, while the firing function can be achieved with the utilization of MTJ during the fabrication process.

**References:**

[1] Z. Hu, Q. Ge, S. Li, L. Jin, and M. Xiong, “Artificial Intelligence Forecasting of Covid-19 in China,” Feb. 2020, Accessed: Jun. 25, 2020. [Online]. Available: http://arxiv.org/abs/2002.07112. [2] R. A. Nawrocki, R. M. Voyles, and S. E. Shaheen, “A Mini Review of Neuromorphic Architectures and Implementations,” IEEE Trans. Electron Devices, vol. 63, no. 10, pp. 3819–3829, 2016, doi: 10.1109/TED.2016.2598413. [3] H. Farkhani, M. Tohidi, S. Farkhani, J. K. Madsen, and F. Moradi, “A Low-Power High-Speed Spintronics-Based Neuromorphic Computing System Using Real-Time Tracking Method,” IEEE J. Emerg. Sel. Top. Circuits Syst., vol. 8, no. 3, pp. 627–638, Sep. 2018, doi: 10.1109/JETCAS.2018.2813389. [4] J. Grollier, D. Querlioz, K. Y. Camsari, K. Everschor-Sitte, S. Fukami, and M. D. Stiles, “Neuromorphic spintronics,” Nat. Electron., 2020, doi: 10.1038/s41928-019-0360-9. [5] A. Sengupta, P. Panda, P. Wijesinghe, Y. Kim, and K. Roy, “Magnetic tunnel junction mimics stochastic cortical spiking neurons,” Sci. Rep., vol. 6, no. July, pp. 1–9, 2016, doi: 10.1038/srep30039.

**Images:**

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/e015896fad0991ac5a8452eee8bf2d23.jpg)
The proposed 3T-MTJ device. Magnetizations of the pinned layers are fixed while that of the MTJ free layer NW can be manipulated by applying electrical current. Conduction electrons are polarized by a pinned layer and push the DW by STT. Neuronal firing happens when the DW propagates past the MTJ device, i.e. when parallel configuration of the MTJ is achieved.

![](https://s3.eu-west-1.amazonaws.com/underline.prod/uploads/markdown_image/1/image/e66f29e5f0d82f3c0bbcc2c2314dc9be.jpg)
(a) Schematic of the NW with the ROI labelled. (b and c) DW position vs time graphs for the reference NW and the result where DWs returned and stabilized around the initial position after neuronal firing. (d) is the case with three pulses sequentially applied. The interval is the same between each pulse, sufficient for DWs to stabilize around the initial position.

Voltage-Gate Assisted Spin-Orbit Torque MRAM for High-Density and Low Power Embedded Applications INVITED

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