United States

NSF Workshop on Micro/Nano Circuits and Systems Design

Probabilistic Computing with p-Bits

technical paper

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


With increasing complexity and heterogeneity of emerging computer systems, fast and accurate design models and tools are critical to support future system designers and application developers in evaluating design options before they can be built. However, traditional simulation-based or analytical models are often too slow or inaccurate to effectively support design processes. This project instead aims to apply advanced machine learning techniques to develop novel predictive modeling and simulation methodologies. We specifically investigate use of advanced machine learning for prediction of power and performance of an application running in a target context based on hardware-dependent and -independent application characteristics obtained by running on any existing other machine. This includes fast and accurate machine learning-based models for: (1) application programmer to predict scaling of application performance or power across different hardware/software implementation options without the need to invest porting or optimizations effort, (2) operating and runtime systems to predict future workload behavior in order to drive runtime optimization decisions, and (3) system architects to predict large-scale application performance and power on different hardware targets during early pre-silicon architectural design space exploration. In this poster, we present an overview of these different project tasks including recent and on-going research efforts and results. 

https://underline.io/speakers/55636-andreas-gerstlauer

Predictive Modeling for Next-Generation Heterogeneous System Design

EM emanations during program execution contain important information about underlying system behavior creating a rich information-bearing side channel that can be used to profile software activity, detect code injections, and optimize software to minimize leakage. Yet there is currently a significant lack of tools for embedded software developers to analyze EM side-channel security of applications on an embedded processor. The only existing capability is based on cumbersome laboratory measurements, which require instrumentation expertise that a typical software engineer lacks, are expensive, provide limited observability, and are slow compared to what a computational tool flow enables. The goal of this project is to develop novel simulation-based approaches for characterization of EM fields emanated by software running on complex embedded processors.

In this poster, we present an overview of the current project status and results. As an initial step towards a tool for simulation-based analysis, we describe a hybrid empirical-simulation flow that uses near-field spatially-localized EM measurements to pre-characterize instruction EM fields and synthesize EM traces for full instruction sequences executed by a software program. In addition, we demonstrate our measurement-based setup and tracing flow for two applications on a 8051-based MCU: (1) evaluation of the vulnerability of the software against EM-based reverse engineering and disassembly of instructions executed by the MCU, and (2) evaluation of observability of program code modifications through out-of-band EM-based malware detection methods.

https://underline.io/speakers/44555-michael-orshansky


Simulation-based Analysis of EM Side Channels in Embedded Systems:From Software to Fields

Non von-Neumann architectures such as in-memory computing (IMC) based on non-volatile memory devices have gained significant interest recently. In this project, we study a tiled, reconfigurable in-memory computing architecture, termed Memory Processing Unit (MPU) based on resistive random-access memory (RRAM) arrays. The tiled architecture allows practical neural networks to be mapped on IMC hardware using realistic RRAM arrays. Device and circuit non-idealities such as finite on/off, negative weight mapping, finite tile size, ADC quantization and device variations have been studies. A general design based on optimized IMC modules and a network-on-chip structure was developed and found to be able to effectively map different network models. The overall system performance has been analyzed and evaluated for different applications.

https://underline.io/speakers/59496-wei-lu



Memory Processing Unit (MPU) - An Efficient, Reconfigurable In-memory Computing Fabric

Energy-Efficient Deep Neural Network Design: From Time-based Circuits to Layer-wise Pruning

https://underline.io/speakers/59497-chris-kim

Energy-Efficient Deep Neural Network Design: From Time-based Circuits to Layer-wise Pruning

The Information Processing Factory (IPF) project aims to exploit self-awareness principles, together with lessons learned from
large-scale factories to contain complexity, achieve predictability and manage robust system design in the context of
autonomous Multi-Processor System-on-Chip (MPSoC) platforms in Cyber-Physical Systems (CPS) and the Internet of
Things (IoT). The goals of the project are to holistically couple key notions of self-awareness, self-organization, and large
scale factory automation to manage the multi-scale and multi-dimensional complexity of emerging MPSoC platforms that
execute dynamic workloads under a multitude of hard and soft constraints. Sensory information at multiple scales -- on-chip,
run-time systems, applications -- will need to be monitored, fused, and interpreted intelligently to assess health status,
mitigate adverse effects, and optimize system goals using a novel hierarchy of self-aware control loops that can both manage
complexity, as well as achieve guarantees. Additionally, the project aims to deploy a unique scalable distributed run-time
Major Activities:
verification (NUVA) architecture that should enable hardware-supported cross-layer monitoring of parametric specifications,
allowing both incorporation of trace-driven historical evidence for model building, as well as run-time execution for model
enhancement. The overall goals of the approach are to synergistically cover the multi-tiered abstraction hierarchy from low level
VLSI circuits to runtime OS and dynamic application software. The project will engage in a unique parallel collaboration
with DFG-funded German partners (at TU Braunschweig and TU Munich), with a dual focus on investigating self-aware IPF
principles for system-on-chip exemplars (US team), as well as for autonomous driving (German team). By leveraging the
German research partners' autonomous driving exemplar, the goal is to demonstrate self-aware IPF principles at multiple,
collaborative scales of autonomy and system design.

https://underline.io/speakers/6768-nikil-dutt

The Information Processing Factory – A Paradigm for Life Cycle Management of Dependable Systems

As Moore's law stalls, novel computing solutions are urgently needed to meet the ever-increasing computing demands from emerging applications such as modern machine learning tasks. With digital techniques running out of steam and emerging technologies pending material revolution, mixed-signal computing which combines circuit techniques in digital, analog, and time domains bring significant opportunities in the near future to dramatically improve computing efficiency.  The benefits of mixed-signal computing include high energy efficiency, compatibility with existing CMOS technology and EDA tools, and strong ties to physical world in a near-sensor or IoT environment.  In this poster, we will briefly discuss the concepts and examples of leveraging the dimensions of “time” in mixed-signal design to accelerate the computing tasks in emerging applications. 

https://underline.io/speakers/59498-jie-gu

Mixed-signal Computing for Emerging Applications

In-memory computing (IMC) SRAM has been demonstrated as a promising technique to significantly improve energy-efficiency for deep neural network (DNN) hardware accelerators. However, designing one involves setting many design variables such as the number of parallel rows to simultaneously activate, analog-to-digital converter (ADC) resolution at the periphery of a memory sub-array, precisions of various parts of a DNN model, etc., which affect energy-efficiency, accuracy, and area. Prior works have not investigated this multi-dimensional design optimization. To fill this knowledge gap, we present an SRAM-based IMC hardware modeling and optimization framework.

https://underline.io/speakers/60043-jae-sun-seo

SRAM-based In-Memory Computing for Energy-Efficient Deep Neural Networks

Bidirectional Brain Computer Interfaces play a key role in our effort to explore the human brain and hold the key to transformative changes in medicine and computing. however, significant barriers remain unaddressed by traditional, circuit-driven approaches. This research applies computational techniques to traditionally analog, mixed-signal and integrated power electronics to advance BBCI technology.

https://underline.io/speakers/59500-visvesh-sathe

Probabilistic Computing with p-Bits

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Probabilistic Computing with p-Bits

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Predictive Modeling for Next-Generation Heterogeneous System Design

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