United States

NSF Workshop on Micro/Nano Circuits and Systems Design

Foundational technologies - Emerging applications from two-dimensional systems and their potential for 3D heterogeneous integration

technical paper

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


With increasing complexity and heterogeneity of emerging computer systems, fast and accurate design models and tools are critical to support future system designers and application developers in evaluating design options before they can be built. However, traditional simulation-based or analytical models are often too slow or inaccurate to effectively support design processes. This project instead aims to apply advanced machine learning techniques to develop novel predictive modeling and simulation methodologies. We specifically investigate use of advanced machine learning for prediction of power and performance of an application running in a target context based on hardware-dependent and -independent application characteristics obtained by running on any existing other machine. This includes fast and accurate machine learning-based models for: (1) application programmer to predict scaling of application performance or power across different hardware/software implementation options without the need to invest porting or optimizations effort, (2) operating and runtime systems to predict future workload behavior in order to drive runtime optimization decisions, and (3) system architects to predict large-scale application performance and power on different hardware targets during early pre-silicon architectural design space exploration. In this poster, we present an overview of these different project tasks including recent and on-going research efforts and results. 

https://underline.io/speakers/55636-andreas-gerstlauer

Predictive Modeling for Next-Generation Heterogeneous System Design

EM emanations during program execution contain important information about underlying system behavior creating a rich information-bearing side channel that can be used to profile software activity, detect code injections, and optimize software to minimize leakage. Yet there is currently a significant lack of tools for embedded software developers to analyze EM side-channel security of applications on an embedded processor. The only existing capability is based on cumbersome laboratory measurements, which require instrumentation expertise that a typical software engineer lacks, are expensive, provide limited observability, and are slow compared to what a computational tool flow enables. The goal of this project is to develop novel simulation-based approaches for characterization of EM fields emanated by software running on complex embedded processors.

In this poster, we present an overview of the current project status and results. As an initial step towards a tool for simulation-based analysis, we describe a hybrid empirical-simulation flow that uses near-field spatially-localized EM measurements to pre-characterize instruction EM fields and synthesize EM traces for full instruction sequences executed by a software program. In addition, we demonstrate our measurement-based setup and tracing flow for two applications on a 8051-based MCU: (1) evaluation of the vulnerability of the software against EM-based reverse engineering and disassembly of instructions executed by the MCU, and (2) evaluation of observability of program code modifications through out-of-band EM-based malware detection methods.

https://underline.io/speakers/44555-michael-orshansky


Simulation-based Analysis of EM Side Channels in Embedded Systems:From Software to Fields

Non von-Neumann architectures such as in-memory computing (IMC) based on non-volatile memory devices have gained significant interest recently. In this project, we study a tiled, reconfigurable in-memory computing architecture, termed Memory Processing Unit (MPU) based on resistive random-access memory (RRAM) arrays. The tiled architecture allows practical neural networks to be mapped on IMC hardware using realistic RRAM arrays. Device and circuit non-idealities such as finite on/off, negative weight mapping, finite tile size, ADC quantization and device variations have been studies. A general design based on optimized IMC modules and a network-on-chip structure was developed and found to be able to effectively map different network models. The overall system performance has been analyzed and evaluated for different applications.

https://underline.io/speakers/59496-wei-lu



Memory Processing Unit (MPU) - An Efficient, Reconfigurable In-memory Computing Fabric

AI/ML and other hardware design - Sustainable Computing via Domain-Specific Architecture and Efficient Circuits

AI/ML and other hardware design - 3D Silicon Brains

Tools and Abstractions: How to Bring IC-like Design Productivity to Buildings and Artificial Living Organisms

Network Design Automation - When Clarke Meets Cerf

Probabilistic Computing with p-Bits

Rapid and Rational Covid-19 Drug-Cocktail Discovery

Can Security be Automatic in Computer Systems?

poster

https://d3smihljt9218e.cloudfront.net/transcript/7699/subtitle/a473bfe245726a1656dc7a2ed6b0cb4f.vtt

English (automatic)

Foundational technologies - Emerging applications from two-dimensional systems and their potential for 3D heterogeneous integration

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Foundational technologies - Emerging applications from two-dimensional systems and their potential for 3D heterogeneous integration

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Next from NSF Workshop on Micro/Nano Circuits and Systems Design

Predictive Modeling for Next-Generation Heterogeneous System Design

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PRESENTATIONS

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COMPANY

RESOURCES

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