Opening session with Sankar	Basu and Margaret Martonosi

**Speakers:**

**Sethuraman Panchanathan**

![](https://assets.underline.io/uploads/markdown_image/1/image/dc14590feb3d46a2d88e3447fbf3ccf0.jpg)

**Margaret Martonosi**

![](https://assets.underline.io/uploads/markdown_image/1/image/87a80dc1dacb65eded0c8e8233127b93.jpg)

**Sankar	Basu**

![](https://assets.underline.io/uploads/markdown_image/1/image/7c43bfae9d4bed69394c2d1a363bea89.jpg)

**Sethuraman Panchanathan Bio**

The Honorable Sethuraman "Panch" Panchanathan is a computer scientist and engineer and the 15th director of the U.S. National Science Foundation (NSF). Panchanathan was nominated to this position by the President of the United States in 2019 and subsequently unanimously confirmed by the U.S. Senate on June 18, 2020. NSF is an $8.3B independent federal agency and the only government agency charged with advancing all fields of scientific discovery, technological innovation and STEM education.

Panchanathan is a fellow of the National Academy of Inventors, where he also served as vice president for strategic initiatives. He is also a fellow of the American Association for the Advancement of Science, the Canadian Academy of Engineering, the Institute of Electrical and Electronics Engineers and the Society of Optical Engineering.


**Margaret Martonosi Bio**

Dr. Margaret Martonosi is the National Science Foundation’s (NSF) Assistant Director for Computer and information Science and Engineering (CISE). While at NSF, Dr. Martonosi is on leave from Princeton University where she has been on the faculty since 1994 and is the Hugh Trumbull Adams '35 Professor of Computer Science. She has also served as Associate Dean of Princeton’s School of Engineering and Applied Science. In 2015-2016, she served within the US Department of State as a Jefferson Science Fellow. From 2017 to 2020, she was Director of Princeton’s Keller Center for Innovation in Engineering Education. 

Dr. Martonosi is a Fellow of the Association for Computing Machinery (ACM) and the Institute of Electrical and Electronics Engineers (IEEE). In addition, her research earned the 2018 IEEE Computer Society Technical Achievement Award, the 2013 Anita Borg Technical Leadership award, and the 2015 Marie R. Pistilli Women in Design Automation award. Her papers have received numerous long-term impact awards from major ACM and IEEE conferences. 

**Sankar Basu Bio**

Sankar Basu is a member of NSF scientific staff and a program Director. He is an elected Fellow of the Institute of Electrical and Electronic Engineers (IEEE), and also of the American Association for the Advancement of Science (AAAS). 

At NSF his primary responsibilities include Micro and Nano- electronic systems and architectures, Cyber Physical Systems (CPS), along with machine learning and neuromorphic hardware design. Over the years, he played leading role in several cross-agency joint initiatives; most recent among them is the "Energy Efficient Computing: from Devices to Architectures" with Semiconductor Research Corporation and the “Real Time Machine Learning Program” with DARPA. In the past, he also served on the National Science and Technology (NSTC) Committee, Office of Science and Technology Policy (OSTP) on Biometrics, and more recently co-chaired an interagency committee on Grand Challenges in Computing.

Introduction

#### **Giovanni De Micheli, EPFL**

![](https://assets.underline.io/uploads/markdown_image/1/image/2e723e2beb8e1d730d0edd1f9d178848.jpg)

#### **Talk Title: Design should be as simple as possible, but not simpler**

Within the various incarnations of computing systems, two groups are going to be significant in the coming decade. High-performance systems exploiting accelerators (ranging from FPGAs to quantum computing) and zero/ultra-low power edge devices. In both cases, there is a plurality of realization technologies that are viable and the choice depends on their cost-effectiveness.

The main show-stopper for early adoption of new devices is the "design" technology. Even when using state-of-the-art CMOS digital design with commercial tools, a successful realization is a major undertaking requiring manpower, complex tool flows and a considerable risk. When considering emerging technologies, the design time, cost and risk are a major roadblock to innovation. These considerations force us to rethink the basic abstractions of computation and composition rules. Simplicity and regularity have been the cornerstone of moving from LSI to VLSI in the eighties. Design automation for complex systems has to release detailed control of some hardware features in view of more global objectives.



#### **Bio**

Giovanni De Micheli is a research scientist in electronics and computer science. He is credited for the invention of the Network on Chip design automation paradigm and for the creation of algorithms and design tools for Electronic Design Automation (EDA). He is Professor and Director of the Integrated Systems Laboratory at EPFL Lausanne, Switzerland. Previously, he was Professor of Electrical Engineering at Stanford University. He was Director of the Electrical Engineering Institute (IEL) at EPFL from 2008 to 2019 and program leader of the Swiss Federal Nano-Tera.ch program. He holds a Nuclear Engineer degree (Politecnico di Milano, 1979), a M.S. and a Ph.D. degree in Electrical Engineering and Computer Science (University of California at Berkeley, 1980 and 1983).

Prof. De Micheli is a Fellow of ACM and IEEE, a member of the Academia Europaea and an International Honorary member of the American Academy of Arts and Sciences. His current research interests include several aspects of design technologies for integrated circuits and systems, such as synthesis for emerging technologies. He is also interested in heterogeneous platform design including electrical components and biosensors, as well as in data processing of biomedical information. He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of ten other books and of over 850 technical articles. His citation h-index is 98 according to Google Scholar. He is member of the Scientific Advisory Board of IMEC (Leuven, B) and STMicroelectronics.

Prof. De Micheli is the recipient of the 2020 IEEE/CEDA Richard Newton Technical Impact Award, the 2019 ACM/SIGDA Pioneering Achievement Award, the 2016 EDAA Lifetime Achievement Award, the 2016 IEEE/CS Harry Goode award for seminal contributions to design and design tools of Networks on Chips, the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools and the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems. He received also the Golden Jubilee Medal for outstanding contributions to the IEEE CAS Society in 2000, the D. Pederson Award for the best paper on the IEEE Transactions on CAD/ICAS in 1987 and 2018, and several Best Paper Awards, including DAC (1983 and 1993), DATE (2005), Nanoarch (2010 and 2012), and Mobihealth(2016).

He has been serving IEEE in several capacities, namely: Division 1 Director (2008-9), co-founder and President Elect of the IEEE Council on EDA (2005-7), President of the IEEE CAS Society (2003), Editor in Chief of the IEEE Transactions on CAD/ICAS (1997-2001). He has been Chair of several conferences, including Memocode (2014) DATE (2010), pHealth (2006), VLSI SOC (2006), DAC (2000) and ICCD (1989).

EDA tools and methodologies - Design should be as simple as possible, but not simpler

#### **Anirudh Devgan, Cadence**

![](https://assets.underline.io/uploads/markdown_image/1/image/80cd459c6957a167c732a17d5e66b2de.jpg)

#### **Talk Title: Computational Software and Future of EDA**

**Bio**

Anirudh Devgan has served as President of Cadence since 2018, overseeing strategy, all research and development for tool and flows, sales, field engineering and customer support, marketing, mergers and acquisitions, and IT. Prior to 2018 he was Executive Vice President and General Manager of the Digital & Signoff and System & Verification groups.

Prior to joining Cadence in 2012, Devgan was General Manager and Corporate Vice President of the Custom Design Business Unit at Magma Design Automation. Previous roles include management and technical positions at IBM, where he received numerous awards including the IBM Outstanding Innovation Award. Devgan is an IEEE Fellow, has written numerous research papers, and holds several patents.

Devgan received a Bachelor of Technology degree in electrical engineering from the Indian Institute of Technology, Delhi, and MS and PhD degrees in electrical and computer engineering from Carnegie Mellon University.


EDA tools and methodologies - Computational Software and Future of EDA

•	Massoud Pedram, USC (Moderator)

•	Shawn Blanton, CMU

•	Andreas Gerstlauer, UT Austin

•	Farinaz Kaushanfar, UC San Diego

•	Wolfgang Kunz, TU Kaiserslautern

•	David Pan, UT Austin

•	Jan Rabaey, UC Berkely


EDA tools and methodologies - Panel Session

Foundational technologies - Emerging applications from two-dimensional systems and their potential for 3D heterogeneous integration

#### **Tsu-Jae King Liu, UC Berkeley**

![](https://assets.underline.io/uploads/markdown_image/1/image/9cff0e43d3c7ed89c22c870a94f1cde0.jpg)

#### **Talk Title: Nano-electro-mechanical switches for future computing paradigms**

The virtuous cycle of integrated-circuit technology advancement has been sustained for over 50 years, resulting in the proliferation of information technology (IT) with transformative impact on all aspects of life in modern society. With the emergence of the Internet of Things (IoT) there is a growing need for edge computing to process data collected locally before communicating information to the cloud. Since most edge computing and IoT devices are wireless, energy efficiency is of paramount importance, and ideally should not come at the cost of degraded functionality. This presentation will discuss how nano-electro-mechanical (NEM) switches can provide for improved energy efficiency and functionality as compared with CMOS transistors that are used for digital computing today. Recent experimental results for NEM switches fabricated using a conventional CMOS back-end-of-line process will be presented. Finally, a new research direction to enable practical Ising machines for greater computational efficiency will be described, as yet another example of how NEM switch technology can help to sustain the IT revolution.

#### **Bio**

Tsu-Jae King Liu was born in Ithaca, New York, and raised in the San Francisco Bay Area. She earned her B.S., M.S. and Ph.D. degrees in electrical engineering at Stanford University in 1984, 1986 and 1994, respectively. She was a scientist at the Xerox Palo Alto Research Center (PARC) before joining the UC Berkeley faculty in 1996 in the Department of Electrical Engineering and Computer Sciences (EECS.

Liu is internationally known in academia and industry for her innovations in semiconductor devices and technology, and is highly regarded for her achievements as an instructor, mentor and administrator. She is a fellow of the Institute of Electrical and Electronics Engineers (IEEE), an elected member of the National Academy of Engineering, a fellow of the National Academy of Inventors, and a board member for Intel Corp. Among her awards are the Ross M. Tucker AIME Electronics Materials Award for seminal work in polycrystalline silicon-germanium thin films, an NSF CAREER Award for research in thin-film transistor technology, the Intel Outstanding Researcher in Nanotechnology Award, the IEEE Aldert van der Ziel Award for distinguished educational and research contributions to the field of electronic devices and materials, and the DARPA Significant Technical Achievement Award for her role in the development of the FinFET, an advanced transistor design used in high-end computer chips.

In addition to excelling in research, Liu has demonstrated a strong commitment to enhancing the educational experience of students. Her dedication earned Liu the EE Division Outstanding Teaching Award, UC Berkeley Distinguished Faculty Mentoring Award and the Semiconductor Research Corporation Aristotle Award.


Foundational technologies - Nano-electro-mechanical switches for future computing paradigms

•	Vijay Narayanan, PSU (Moderator)

•	Keren Bergman, Columbia

•	Sayeef Salahuddin, UC Berkeley

•	Dmitri Strukov, UCSB

•	Jian-Ping Wang, University of Minnesota

•	Phil Wong, Stanford

•	Todd Younkin, SRC


Foundational technologies - Panel Session

Day 1 closing remarks from Sankar	Basu

**Speaker:**

**Sankar	Basu**

![](https://assets.underline.io/uploads/markdown_image/1/image/7c43bfae9d4bed69394c2d1a363bea89.jpg)

**Bio**

Sankar Basu is a member of NSF scientific staff and a program Director. He is an elected Fellow of the Institute of Electrical and Electronic Engineers (IEEE), and also of the American Association for the Advancement of Science (AAAS). He came to NSF from the IBM T. J. Watson Research Center. He received a PhD from the University of Pittsburgh, served on the faculty of Stevens Institute of Technology, and was a visiting senior scientist Naval Underwater Systems Center, CT. He visited the Ruhr University, Bochum, Germany as an Alexander von Humboldt fellow, and the MIT Laboratory for Information and Decision Systems (LIDS) for extended periods. During the summer of 2012 he was a science advisor to the US Embassy in Berlin, Germany as a State Department Embassy Science Fellow. In recent years, he has also visited the Wroclaw University of Science and Technology, Poland.

At NSF his primary responsibilities include Micro and Nano- electronic systems and architectures, Cyber Physical Systems (CPS), along with machine learning and neuromorphic hardware design. He has been involved in several interdisciplinary programs at NSF, e.g., National Nanotechnology Initiative (NNI), Interactions between Mathematics and Computer Science (MCS), Science of Learning Centers (SLC), and the Information Technology Research (ITR) program. Over the years, he played leading role in several cross-agency joint initiatives; most recent among them is the "Energy Efficient Computing: from Devices to Architectures" with Semiconductor Research Corporation and the “Real Time Machine Learning Program” with DARPA. In the past, he also served on the National Science and Technology (NSTC) Committee, Office of Science and Technology Policy (OSTP) on Biometrics, and more recently co-chaired an interagency committee on Grand Challenges in Computing.

Dr. Basu's own research interests had been in the analytical aspects circuits, systems and signal processing. At IBM, he worked on statistical machine learning, speech and multimedia data retrieval, and has extensively published on filter synthesis, image processing, nonlinear modeling techniques. An author/coauthor of over one hundred refereed publications including coediting two special volumes on Wavelets and Filter Banks, and a book Advances in Learning Theory: Methods, Models, and Applications, he has given several keynote speeches at the International Conferences and Workshops in the general areas of Signal and Systems Theory, and Computing Hardware design. He holds 10 US Patents.

He was the Editor-in-Chief (EiC) for IEEE Transactions on Circuits and Systems  - Parts I & II for a period of 6 years, and has served in editorial capacities for a number of publications including the Proceedings of the IEEE, IEEE Transactions on Multimedia, the Journal of Applied Signal Processing of the European Association of Signal Processing, the Journal of VLSI Signal and Image Processing published by the Kluwer Academic Publishers. He also served on the Editorial Board of IEEE Press. At present, he serves on the editorial board of the Journal of Multidimensional Systems and Signal Processing published by Springer. Most recently he coedited a 2-volume special issue of the IEEE Proceedings on Non-silicon non-von Neumann computing.

Dr. Basu has organized, chaired sessions, and has been a panelist in many conferences in the areas of computing, circuits and systems, statistical learning theory. He was the founding general chair and a steering committee member of the first IEEE International Conference on Multimedia & Expo (ICME), which has since become a major international conference. He was a also co-organizer of the NATO Advanced Study Institute on Statistical Learning and Applications at the Katholieke University, Leuven, Belgium.

Day 1 Closing Remarks 

Day 2 Opening Session with Sankar Basu and Rance Cleveland

**Speaker:**


**Rance Cleaveland - Division DIrector NSF**

![](https://assets.underline.io/uploads/markdown_image/1/image/aa9af3f41ffc57ee0a3343191e078d06.jpg)

**Sankar	Basu**

![](https://assets.underline.io/uploads/markdown_image/1/image/7c43bfae9d4bed69394c2d1a363bea89.jpg)

**Rance Cleaveland Bio**

Rance Cleaveland is Professor of Computer Science at the University of Maryland (UMD) at College Park. Since 2018, he has also been serving as Division Director of the Computing and Communication Foundations (CCF) division within the Computer and Information Science and Engineering (CISE) directorate of the National Science Foundation. From 2005 to 2014 he held the position of the Executive and Scientific Director of the Fraunhofer USA Center for Experimental and Software Engineering in College Park. 

Prior to joining the UMD faculty in 2005, he had professorships at the State University of New York at Stony Brook and at North Carolina State University (NCSU). He is a co-founder, past CEO and current chairman of the board of Reactive Systems, Inc., a company that makes model-based testing tools for embedded software, and a past recipient of National Young Investigator Awards from the National Science Foundation and the Office of Naval Research and the Alcoa Engineering Research prize from North Carolina State University. He has also won undergraduate teaching awards from UMD and NCSU. He has published over 140 papers in the areas of software verification and validation, formal methods, model checking, software specification formalisms, verification tools, software testing, and software architecture. 

**Sankar Basu Bio**

Sankar Basu is a member of NSF scientific staff and a program Director. He is an elected Fellow of the Institute of Electrical and Electronic Engineers (IEEE), and also of the American Association for the Advancement of Science (AAAS). 

At NSF his primary responsibilities include Micro and Nano- electronic systems and architectures, Cyber Physical Systems (CPS), along with machine learning and neuromorphic hardware design. Over the years, he played leading role in several cross-agency joint initiatives; most recent among them is the "Energy Efficient Computing: from Devices to Architectures" with Semiconductor Research Corporation and the “Real Time Machine Learning Program” with DARPA. In the past, he also served on the National Science and Technology (NSTC) Committee, Office of Science and Technology Policy (OSTP) on Biometrics, and more recently co-chaired an interagency committee on Grand Challenges in Computing.

Day 2 Opening Session

#### **William Dally, NVIDIA**

![](https://assets.underline.io/uploads/markdown_image/1/image/a0ac52417af5a095e3c1418839483e7e.jpg)

#### **Talk Title: Sustainable Computing via Domain-Specific Architecture and Efficient Circuits**

#### **Bio**

Bill Dally joined NVIDIA in January 2009 as chief scientist, after spending 12 years at Stanford University, where he was chairman of the computer science department. Dally and his Stanford team developed the system architecture, network architecture, signaling, routing and synchronization technology that is found in most large parallel computers today. Dally was previously at the Massachusetts Institute of Technology from 1986 to 1997, where he and his team built the J-Machine and the M-Machine, experimental parallel computer systems that pioneered the separation of mechanism from programming models and demonstrated very low overhead synchronization and communication mechanisms. From 1983 to 1986, he was at California Institute of Technology (CalTech), where he designed the MOSSIM Simulation Engine and the Torus Routing chip, which pioneered “wormhole” routing and virtual-channel flow control. He is a member of the National Academy of Engineering, a Fellow of the American Academy of Arts & Sciences, a Fellow of the IEEE and the ACM, and has received the ACM Eckert-Mauchly Award, the IEEE Seymour Cray Award, and the ACM Maurice Wilkes award. He has published over 250 papers, holds over 120 issued patents, and is an author of four textbooks. Dally received a bachelor's degree in Electrical Engineering from Virginia Tech, a master’s in Electrical Engineering from Stanford University and a Ph.D. in Computer Science from CalTech. He was a cofounder of Velio Communications and Stream Processors.


AI/ML and other hardware design - Sustainable Computing via Domain-Specific Architecture and Efficient Circuits

 Electronic design and design automation (EDA) is a key enabling technology in the advancement of information processing that we are enjoying today. EDA has provided fundamental design principles and tools empowering the exponential growth of the number of transistors on an integrated circuit chip over the past 50 years. Without EDA, it would not have been possible for billion-transistor chips to be a reality! 

After five decades of growth, the field of EDA now faces some unique challenges. On one hand, we are approaching the physical limit of transistor scaling, and the golden days of exponential growth in transistor density are over. The exorbitant cost of integrated circuit fabrication and the excessive complexity of EDA tools make it difficult to bring design automation innovations to practice. On the other hand, the recent rise of machine learning and artificial intelligence applications and emerging architectures and technologies calls for more customized solutions to designing electronic systems. 

## **Objectives of the Workshop:**

This workshop, funded by the National Science Foundation (NSF), will assemble a diverse group of leading researchers from both academia and industry to identify future research directions in design and design automation of electronic systems and architectures in response to the challenges and opportunities. It will feature plenary talks and panels as well as roundtable discussions. Collectively, the workshop attendees will explore answers to overarching questions such as 

•	what are the high-risk and high-return research topics, 

•	what other fields adjacent to EDA research should be aggressively pursued for highly interdisciplinary collaboration, and

•	where the research funding should come from and how it should be distributed to encourage more transformative research. 

The workshop will also include a satellite event with a roundtable panel discussion on strategies to improve foundry access to US-based EDA researchers. A final report, based on the deliberations of the workshop, will be produced to the government recommending future research directions.


NSF Workshop on Micro/Nano Circuits and Systems Design

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