SPEAKERS/OTITOALEKE AKINOLA
Otitoaleke Akinola

Otitoaleke Akinola

University of Texas

Otitoaleke's lectures

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INTERMAG 2021

GB-02 - Domain Wall-Magnetic Tunnel Junction Spin Orbit Torque Devices for In-Memory Computing

Abstract:

There are many potential applications for spintronics including in-memory, neuromorphic, and radiation hard computing. In- memory computing offers a solution to the memory wall bottleneck that hinders traditional architectures. Neuromorphic computing has the potential to revolutionize how data-intensive tasks, such as image recognition, are computed by emulating how a biological brain operates. Radiation hard computing is useful for certain situations, mainly space applications, where the Earth’s atmosphere does not protect sensitive CMOS hardware. All of these applications can be achieved using domain wall motion-based devices. The domain wall magnetic tunnel junction (DW-MTJ) device architecture is explored in this work as shown in figure 1. DW-MTJ devices operate by sending a current pulse along a ferromagnetic wire to propagate a domain wall from the input to the output of the device. As the domain wall passes under the MTJ, the magnetization state of the bottom layer of the CoFeB/MgO/CoFeB junction changes. By controlling where the domain wall is, the MTJ can have programmable resistance. We use current driven domain wall motion to electrically switch the devices. It has been shown that spin logic requires high tunneling magnetoresistance, low switching voltages, and high stability. These hurdles have been overcome in this work by utilizing perpendicular anisotropy, spin orbit torque switching, and optimized fabrication. Incorvia et al. in 2015 demonstrated that information could be encoded in a magnetic wire by moving a domain wall, but the TMR of those devices was 12% 1. Here, we develop a process that maintains as much TMR as possible, achieving TMR > 150%, as well as no reduction in resistance-area (RA) product after device fabrication. There were several improvements made to the previous fabrication process. The main change was to remove the reactive ion etch step to contact the MTJ. Incorvia et al. opened a via in polymethylmethacrylate (PMMA) and then used a CF4 reactive ion etch through a hydrogen silsesquioxane (HSQ) layer to expose the MTJ and wire contacts. In our new process, we replaced this step with a negative tone resist and encapsulation step to achieve the same result of an open via to the MTJ and domain wall track without exposing the sensitive layers to a reactive etch. This way the MTJ is never directly exposed: during all etches and encapsulation, the MgO is protected by negative resist. Furthermore, the encapsulation was performed at relatively low temperatures of 100 °C to prevent any additional loss of TMR, and silicon nitride was used instead of silicon oxide to reduce oxidation. These factors allowed our devices to maintain their high TMR post-processing. The TMR is shown in the field loops of four devices in figure 2. The average achieved was 164±17%, compared to the unpatterned film TMR of 168±6%. Before fabrication, the film had RA = 35±2 Ω-μm2 and the devices have RA = 31±3 Ω-µm2. This indicates that our fabrication process had little to no negative impact on the magnetic integrity of our material. These devices utilize electrical initialization of domain walls rather than an external magnetic field, so they can be fabricated as straight wires rather than curved. This allows for increased density if this technology becomes industrialized. Previous iterations of these devices were curved to allow an external magnetic field to nucleate a domain wall at an initial position. Here, we opted for an electrical approach by implementing an oersted field line near the left contact of each device. A short pulse is sent through this line which nucleates a domain wall in the ferromagnetic track 2. This is one step closer towards all electric operation of the memory-in-logic devices. These oersted field lines increased stability and repeatability by nucleating the domain wall in the same position each time, rather than an unpredictable location via external magnetic field nucleation. Calculating the variability based on the switching voltage range over 10 cycles with both nucleation methods showed an improvement from external magnetic field (105%) variability to the oersted field line (7%) variability. We show in simulation that these improvements bring the variability of the technology within the regime for large circuit function such as a 32-bit full adder 3. Partial funding from Sandia National Lab (SNL). SNL is managed and operated by NTESS under DOE NNSA contract DE-NA0003525.

References:

1J. A. Currivan-Incorvia, S. Siddiqui, S. Dutta, E. R. Evarts, C. A. Ross & M. A. Baldo. 2015 IEEE Int. Electron Devices Meet. 32–36 (2015)
2G. Zahnd, V. T. Pham, A. Marty, M. Jamet, C. Beigné, L. Notin, C. Vergnaud, F. Rortais, L. Vila & J. P. Attané. J. Magn. Magn. Mater. Vol. 406, p. 166–170 (2016)
3T. Patrick Xiao, M. J. Marinella, C. H. Bennett, X. Hu, B. Feinberg, R. Jacobs-Gedrim, S. Agarwal, J. S. Brunhaver, J. S. Friedman & J. A. C. Incorvia. IEEE J. Explor. Solid-State Comput. Devices Circuits., Vol. 5, p. 188-196 (2019)

Images:

Fig.1: Top-down SEM image of a DW-MTJ device. Patterned domain wall track (labeled DW track) and magnetic tunnel junction (labeled MTJ) identified. Device width (labeled w) is 450 nm. Widths down to 250 nm were patterned and tested.

Fig. 2: Field loop for devices in this work. RMTJ is the measured resistance through the tunnel junction. Spin-orbit torque current switching was also performed and will be presented.

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MMM 2020

A5-02 Online Training of Spiking Neural Networks Using Domain Wall Magnetic Tunnel Junction Synapses

Authors: O.G. Akinola, B. Mendawar, J.C. Incorvia, Electrical and Computer Engineering, The University of Texas at Austin, Austin, Texas, UNITED STATES|C.H. Bennett, M.J. Marinella, Sandia National Laboratories, Albuquerque, New Mexico, UNITED STATES|X. Hu, J.S. Friedman, Electrical and Computer Engineering, The University of Texas at Dallas, Richardson, Texas, UNITED STATES|

Abstract Body: Progress has been made on emulating the neuron and the synapse using magnetic devices 1, 2 especially with three-terminal magnetic tunnel junctions (3T-MTJs) 3, 4. Increasingly more accurate biological mimics are being developed with the 3T-MTJ like the Leaky-Integrate-Fire (LIF) 5 neuron displaying lateral inhibition, and the 3T-MTJ synapse model showing spike timing dependent plasticity (STDP) 6, 7. However, more work must be done to achieve real-time machine learning. Using an earlier developed synapse circuit 8 and a 3T-MTJ spice model 9, we show the transient behavior of a 2 by 2 crossbar array (cartoon in Fig 1). There is STDP for different delay conditions between the pre- and post-synaptic neural spikes. The shorter the time difference between the onset of the pre- and post-synaptic neuron spike, the higher the current through the ferromagnet (Fig 2). Higher current leads to higher rate of change of the domain wall (DW) position per neural event and higher DW displacement. At t=0, the initial pair of presynaptic and postsynaptic pulses helps to randomly give the DWs a head start. DW for synapse S2 (red plot) rises faster because it has the least delay of 1 ns between its pre- and post-synaptic pulse despite its pulses lagging that of S1 whose DW had a head start. Scaling this up, the 3T MTJ synapse is robust in more complex systems such as a machine learning clustering task.References: 1 S. Lequeux et al., Sci. Rep., vol. 6, no. August, 2016, doi: 10.1038/srep31510. 2 J. Torrejon et al., Nature, vol. 547, no. 7664, pp. 428–431 (2017) 3 N. K. Upadhyay, H. Jiang, Z. Wang et al, Adv. Mater. Technol., vol. 1800589, pp. 1–13 (2019) 4 N. Hassan et al., J. Appl. Phys., vol. 124, no. 15, p. 152127 (2018) 5 G. Bi and M. Poo, Annu. Rev. Neurosci., vol. 24, no. 1, pp. 139–166 (2002) 6 H. Markram, W. Gerstner, and P. J. Sjöström, Front. Synaptic Neurosci., vol. 4, pp. 2–5 (2012) 7 O. Akinola, X. Hu, C. H. Bennett et al, J. Phys. D. Appl. Phys., vol. 52, no. 49 (2019) 8 X. Hu, A. Timm, W. H. Brigner et al, IEEE Trans. Elect. Dev., vol. 66, no. 6, pp. 2817–2821 (2019)

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