**Please read the paper on the following link:**

https://1worldcontent.com/ess/9281.pdf

**Abstract:**

In this work, experimental assessment of the variability of threshold voltage and drain current in junctionless nanowire nMOS transistors is presented. Die-to-die variability of threshold voltage and drain current is presented and compared to inversion mode nanowire with the same dimensions. Although the junctionless nanowires have shown larger threshold voltage matching coefficients than inversion mode devices, the variability obtained experimentally has shown to be smaller than predicted by some simulations reported in the literature. Also, it has been shown that as the channel length of junctionless nanowire transistors is reduced, the current variability becomes smaller than in inversion mode nanowires, at the same current level and dimensions.

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9199382

**Abstract:**

The Von-Neumann bottleneck is a clear limitation for data-intensive applications, bringing in-memory computing (IMC) solutions to the fore. Since large data sets are usually stored in nonvolatile memory (NVM), various solutions have been proposed based on emerging memories, such as OxRAM, that rely mainly on area hungry, one transistor (1T) one OxRAM (1R) bit-cell. To tackle this area issue, while keeping the programming control provided by 1T1R bit-cell, we propose to combine gate-allaround stacked junctionless nanowires (1JL) and OxRAM (1R) technology to create a 3-D memory pillar with ultrahigh density. Nanowire junctionless transistors have been fabricated, characterized, and simulated to define current conditions for the whole pillar. Finally, based on Simulation Program with Integrated Circuit Emphasis (SPICE) simulations, we demonstrated successfully scouting logic operations up to three-pillar layers, with one operand per layer.

Ultrahigh-Density 3-D Vertical RRAM with Stacked Junctionless Nanowires for In-Memory-Computing Applications

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9213.pdf

**Abstract:**

In this work, a wafer-scale fabrication of biologically sensitive Si nanowire FET is demonstrated for pH sensing and electrical detection of DNA hybridization. Based on conventional “top-down” CMOS compatible technology, our bioFETs explore a wide range of design (nanowires (NW), nanoribbons (NR), and honeycomb (HC) structures) with opening access scaled down to only 120 nm. After device fabrication, IDS-VBG transfer and IDS-VDS output characteristics show a conventional n-type FET behavior with an ION/IOFF value higher than 105, as well as an increase of threshold voltage (VTH) as the NW width is reduced. Then, using a capacitive coupling in our dual-gated Si bioFETs, the pH sensitivity is enhanced with a pH response up to 600 mV/pH. Finally, the increase of threshold voltage of n-type SiNWs due to the hybridized target DNA molecules is successfully detected

Wafer-Scale Fabrication of Biologically Sensitive Si Nanowire FET: From pH Sensing to Electrical Detection of DNA Hybridization

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9204657

**Abstract:**

In this work, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film siliconon-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: the Effect of Back Bias on Drain Current and Transconductance

**Session Chairs:** Gianluca Fiori, University of Pisa; Max Lemme, AMO GmbH and RWTH Aachen University

D1L-5: Advanced Devices & Processing

technical paper

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021 
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021 
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021 
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021 
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**

To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

ESSCIRC ESSDERC 2021

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





**Session Chairs:** Nitin Chawla, STMicroelectronics; Elisa Vianello, CEA-Leti

D3L-1: In/Near-Memory Computing (JOINT 2020 TEDbrief special edition & SSC-L special edition)

**Session Chairs:** Francis Calmon, Institut National des Sciences Appliquées de Lyon; Radu Sporea, University of Surrey

D3L-6: Emerging Sensor Technologies

**Session Chairs:** Sorin Voinigescu, University of Toronto; David Esseni, University of Udine

Sylvain Barraud

5

8

Presentations

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Ultrahigh-Density 3-D Vertical RRAM with Stacked Junctionless Nanowires for In-Memory-Computing Applications

Wafer-Scale Fabrication of Biologically Sensitive Si Nanowire FET: From pH Sensing to Electrical Detection of DNA Hybridization

Cryogenic Operation of Thin-Film FDSOI nMOS Transistors: the Effect of Back Bias on Drain Current and Transconductance

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