Italy

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9171283

**Abstract:**

This work presents a simplex and a full duplex digital communication interface that enhance the energy efficiency of chip-to-chip digital communication in low speed low power systems. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5^10-12. The simplex and full duplex interfaces achieve an energy consumption of 0.38pJ/b and 1.2pJ/b respectively. The simplex interface achieves a power reduction of 2× to 27× compared to conventional LVCMOS for data rates from 10kb/s to 50Mb/s. The full duplex interface achieves a power reduction of 5× to 11× for data rates from 100kb/s to 50Mb/s.

ESSCIRC ESSDERC 2021

A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

adaptable

full duplex

digital communication interface

chip-to-chip

energy efficiency

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.

Highlights:
* 3 joint keynote presentations
* 3 keynote presentations ESSCIRC
* 3 keynote presentations ESSDERC
* Invited papers with overall coverage of all aspects of advanced devices and circuits
* Presentation of IEEE and ESSCIRC/ESSDERC Awards
* Educational Events

JOINT PLENARY talks live broadcast: September 13, 2021<br>
ESSCIRC and ESSDERC KEYNOTE talks live broadcast: September 15, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Conference Technical sessions: September 14 – 16 – 17, 2021<br>
LIVE Q&A INTERACTIVE sessions for all Educational Events: September 20-21-22, 2021<br>
(on demand videos available from September 6 until November 30, 2021)

**Please see here for the [ESSCIRC Guide](https://drive.google.com/file/d/10dghzuv4aQBty4QfTIY9Q8hXyqsue8Le/view?usp=sharing), [ESSDERC Guide](https://drive.google.com/file/d/10dx9y2tm9cHPDa4upNUYjfXCf44aPry5/view?usp=sharing), and the [Program at a Glance](https://drive.google.com/file/d/10eU0OLTXEpiNzI5hkqv4mSr43T8cedPP/view?usp=sharing)**


To access ESSCIRC ESSDERC 2021, you must pre-register for the conference.  Instructions on how to access the event will be provided directly to attendees and included on the ESSCIRC ESSDERC conference website. [Register now](https://www.esscirc-essderc2021.org/).

Please register for the ESSCIRC conference to join the event.

The aim of ESSCIRC and ESSDERC is to provide an annual European forum for the presentation and discussion of recent advances in solid-state devices and circuits.
The level of integration for system-on-chip design is rapidly increasing.

This is made available by advances in semiconductor technology. Therefore, more than ever before, a deeper interaction among technologists, device experts, IC designers, and system designers is necessary. ESSCIRC and ESSDERC are governed by a common Steering Committee and share Plenary Keynote Presentations and Joint Sessions bridging both device and circuit communities.





technical paper

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9173.pdf

**Abstract:**

This paper demonstrates a compact BLE transmitter (TX) achieving fully on-chip integration and high system-efficiency. This BLE TX is constructed based on a 1.2 GHz 8phases current-reused ring oscillator (RO) with a digital phase-locked loop (PLL). To mitigate the spurious emission, including HD2 caused by phase mismatches, an edge-timing calibration is proposed by reusing the digital PLL in this paper. A transformer-based Class-D PA with implicit LC-notch is implemented to improve the system efficiency with higher harmonic suppression for both HD2 and HD3 with a compact on-chip area. The presented TX supports both 1 Mbps and 2 Mbps GFSK modulation with low power consumption.

A 0.25mm² BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9187.pdf

**Abstract:**

A low power multi-mode transceiver IC is presented to support 802.11b/g/n/ax, Bluetooth classic (BT) and low energy (BLE). The design features two signal paths and one merged RF port, demonstrating the first combo chip optimized for low power IoT applications. With the proposed power saving architecture, the combo chip presents comparable or better performance against standalone solutions. The receiver chain noise figure (NF) is measured at 2.7dB in 802.11ax mode, and the power consumption is 32mW, the lowest reported in its class. In BLE receiving mode, NF is 5dB while consuming 9.7mW. The measured 802.11 mask compliant output power is 21.5dBm with 22%/20% PA/Tx efficiency. With 1024-QAM OFDM (MCS11) signals, -35dB EVM is achieved at 16dBm output power without digital pre-distortion (DPD). EVM floor reaches -42dB with 11n MCS7 signals. As for BLE transmission, 10.5dBm power can be delivered with 28%/21% PA/Tx efficiency. Implemented in 22nm CMOS technology, the entire radio occupies 2.1mm^2 silicon area.

A Highly Efficient Combo Transceiver for 802.11b/g/n/ax and BT/BLE in 22nm CMOS

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9161.pdf

**Abstract:**

This paper presents a transmitter concept which generates a wide coherent modulation bandwidth. The proposed FDDAC based Tx concept exploits the relation between the discrete and continuous-time Fourier Transform leading to intrinsic Nyquist filtering. Thus, the sampling rates in the analogue-mixed-signal and the DSP domains are reduced by up to two orders of magnitude compared to conventional Txs. The experimentally verified integrated Tx-IC for 802.11ad/y applications generates a single-carrier 16QAM signal with a modulation BW of up to 2GHz. The measured EVM values are 7.2% and 11.8% for a 1 and 2GHz QPSK signal, respectively, whereas they are 9.6% and 13.9% for a 1 and 2GHz-wide 16QAM signal.

FDDAC-Based Transmitter with 2 GHz Modulation Bandwidth and 8 Gbit/s Data Rate

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9113.pdf

**Abstract:**

Noise-shaping is essential for Direct Digital to RF (DDRF) transmission but filtering of Out of Band (OOB) quantization noise is difficult at 6 GHz for Wi-Fi 6E. We present a filter-free DDRF architecture that introduces targeted noise-shaping (TaNS) to meet the spectral mask. TaNS attenuates quantization noise at offsets between one and ten times the bandwidth by moving it far out-of-band. The prototype is fabricated in 28nm CMOS with an active area of 0.022 mm2 and shows the feasibility of 64-QAM modulation up to 281 Mbps.

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9157.pdf

**Abstract:**

As wireline transceivers continue to push for higher speeds, their power consumption becomes increasingly more critical. This paper describes methods that can reduce the power drawn by drivers and multiplexers on the transmit side and equalizers and clock and data recovery circuits on the receive side. These concepts have been incorporated in designs ranging from 40 Gb/s to 80 Gb/s in 45-nm and 28-nm process nodes.

Low-Power Techniques for Wireline Systems

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9168.pdf

**Abstract:**

This paper describes a 56Gbaud 7bit DAC based transmitter demonstrating data-rates of 112Gb/s, 145Gb/s and 168Gb/s in PAM4, PAM6, and PAM8 respectively. The transmitter with 1.2Vppd high-swing driver is implemented in a 7nm FinFET process. The power efficiency is 1.5pJ/b (PAM4) & 1.0pJ/b (PAM8).

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET

**Please read the paper on the following link:**

https://1worldcontent.com/ess/9134.pdf

**Abstract:**

This article presents a 64-Gb/s PAM-4 TX with a proposed 4-tap hybrid feed-forward equalization (FFE). The pre-emphasis (PE) based FFE is employed to enlarge the output swing by directly stacking the distorted pulses on the main pulse. And it consumes less power than the de-emphasis (DE) based counterpart as it only boosts the desired distorted symbols. The fractionally-spaced (FS) based FFE provides compensation of signal beyond Nyquist and the post2 tap compensates for the lower-frequency signal, the combination of them realizes an accurate equalization and wide compensation range.

A 1.4-Vppd 64-Gb/s PAM-4 Transmitter with 4-Tap Hybrid FFE Employing Fractionally-Spaced Pre-Emphasis and Baud-Spaced De-Emphasis in 28-nm CMOS

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9178737

**Abstract:**

A continuous-time band-pass (BP) delta-sigma (DS) analog-to-digital converter (ADC) is presented in this work. The proposed BP ADC has four time-interleaved (TI) sub-ADCs that use ring-oscillators as phase-domain integrators to achieve second-order noise shaping. The proposed BP-ADC architecture ensures that spurious tones due to mismatch between sub-ADCs fall out of signal-band and also has intrinsic interferer rejection capability. A prototype ADC fabricated in 65nm CMOS is operated at an IF of 52MHz. The ADC has an SNDR of 63.1dB and 59.5dB at 1.04MHz and 4.3MHz bandwidth, respectively. The ADC consumes only 0.36mW power from a 0.9V supply and has an energy efficiency of 21fJ/step improving upon the current state-of-the-art by 3.5x.

21fJ/Step OTA-Less, Mismatch-Tolerant Continuous-Time VCO-Based Band-Pass ADC

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9137304

**Abstract:**

This paper introduces a novel SAR-based algorithm that speeds up the conversion by using two digital-to-analog converters that operate in a ping-pong fashion. It has been implemented in a 4x time-interleaved analog-to-digital converter in a 16-nm FinFET technology. Each channel uses the proposed ping-pong SAR (PP-SAR) algorithm in a coarse phase followed by a comparator-based asynchronous binary search (CABS) fine phase to realize 418 MHz/channel 10-bit conversion with 51-dB SNDR at Nyquist. The total power consumption is 7.9 mW corresponding to a Walden FoM of 16 fJ/conversion-step at Nyquist.

A 1.67-GSps Ti 10-Bit Ping-Pong SAR ADC with 51-dB SNDR in 16-nm FinFET

**Please read the paper on the following link:**

https://ieeexplore.ieee.org/document/9183905

**Abstract:**

This letter presents a compact buffer-less 12-bit output SAR-based bridge-to-digital converter. Eliminating the sample-and-hold circuit substantially simplifies the sensor front-end by providing a high impedance input stage. The binary weighted digital-to-analog converter (DAC) is replaced with a switched-capacitor DAC which is driven by an error-feedback modulator. This alleviates mismatch issues and provides area and power savings when used with a Wheatstone bridge as a read-out. The converter has a wide input range of 830 mV making it suitable for gas sensor applications. It is realized in 65-nm CMOS, occupies 0.01 mm2 area, and consumes 6.2 μA with a 45 ms conversion time. It achieves 9.1 ENOB for a DC input and a Walden FoM of 0.65 nJ/conv-step.

A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

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A 0.25mm² BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration

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TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping

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A 0.38pJ/B Simplex and a 1.2pJ/B Full Duplex Chip-to-Chip Digital Communication Interface with Data Rate and Load Capacitance Adaptability

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Next from ESSCIRC ESSDERC 2021

A 0.25mm² BLE Transmitter with Direct Antenna Interface and 19% System Efficiency Using Duty-Cycled Edge-Timing Calibration

Similar lecture

TaNS-DDRF: A 160-MHz Bandwidth 6-GHz Carrier Frequency Digital-Direct RF Transmitter for Wi-Fi 6E with Targeted Noise-Shaping

Stay up to date with the latest Underline news!

PRESENTATIONS

CONFERENCES

COMPANY

RESOURCES

Downloads